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AR# 52313

LogiCORE IP Aurora 64B66B v7.3 (ISE 14.3/Vivado 2012.3), v7.3Rev1 (Vivado 2012.4) - Release Notes and Known Issues

Description

This answer record contains the Release Notes for the Aurora 64B66B v7.3 Core released in ISE 14.3 and Vivado 2012.3 design tools, and v7.3Rev1 core released in Vivado 2012.4 design tools, and includes the following:

  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide

Solution

New Features

ISE Design Suite:

v7.3

  • Zynq family support
  • Hot-plug support for 7 series
  • HDL naming guideline
  • ISE 14.3 design tools support

Vivado Design Suite:

v7.3 Rev1

  • 2012.4 design tools support
  • Auto-upgrade feature

v7.3

  • 2012.3 design tools support
  • Hot-plug support for 7 series
  • HDL naming guideline

Supported Devices

ISE Design Suite:

Zynq
Virtex-7
Virtex-7 Low Voltage (-2L)
Defense Grade Virtex-7Q (XQ)
Defense Grade Virtex-7Q Low Voltage (XQ,-2L)

Kintex-7
Kintex-7 Low Voltage (-2L)
Defense Grade Kintex-7Q (XQ)
Defense Grade Kintex-7Q Low Voltage (XQ,-2L)

Virtex-6 CXT/LXT/SXT/HXT
Virtex-6 Lower Power (-1L) LXT/SXT
Defense Grade Virtex-6Q (XQ) LXT/SXT
Defense Grade Virtex-6Q Lower Power (XQ,-1L) LXT/SXT

Vivado Design Suite:

Virtex-7
Virtex-7 XT
Virtex-7 HT
Virtex-7 Low Voltage (-2L)
Defense Grade Virtex-7Q (XQ)
Defense Grade Virtex-7Q Low Voltage (XQ,-2L)

Kintex-7
Kintex-7 Low Voltage (-2L)
Defense Grade Kintex-7Q (XQ)
Defense Grade Kintex-7Q Low Voltage (XQ,-2L)

Resolved Issues

ISE Design Suite:

v7.3

  • Data loss in single bead transfers within rxcrc module
  • HDL Naming conflict issue

Vivado Design Suite:

v7.3

  • Tool is generating unwanted .txt file when the IP is generated
  • Data loss in single bead transfers within rxcrc module
  • HDL Naming conflict issue

v7.3 Rev1

  • Updated VCO calculation for 7 series FPGA GTX/GTH designs

Known Issues

ISE Design Suite:

v7.3

  1. AXI4_LITE based DRP interface is not fully AXI4_LITE compliant
    Description: AXI4_LITE to DRP is port mapped and is not native AXI4_LITE
  2. Hot Plug circuit not verified for Virtex-7 GTH devices
    Description: Hot Plug circuit not verified on board for Virtex-7 GTH devices
  3. RX Reset Sequence Requirement for Production Silicon mentioned in (Xilinx Answer 53561) for Artix-7 GTP transceivers is not implemented in v7.3 of the core.
  4. RX Reset Sequence Requirement for Production Silicon mentioned in (Xilinx Answer 53779) for Virtex-7 GTH transceivers is not implemented in v7.3 of the core.


    Vivado Design Suite:

    v7.3

    1. AXI4_LITE based DRP interface is not fully AXI4_LITE compliant
      Description: AXI4_LITE to DRP is port mapped and is not native AXI4_LITE
    2. Hot Plug circuit not verified for Virtex-7 GTH devices
      Description: Hot Plug circuit not verified on board for Virtex-7 GTH devices


    v7.3 Rev1

    Auto-upgrade feature is enabled from Aurora 64B66B v7.2 core

    Description: Aurora 64B66B core can be upgraded from v7.2 of the core

    The most recent information, including known issues, work-arounds, and resolutions for this version is provided in the IP Release Notes Guide located at:
    http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf

AR# 52313
Date Created 10/10/2012
Last Updated 05/30/2013
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2012.3
  • ISE Design Suite - 14.3
IP
  • Aurora 64B/66B