Here is an example of memory created using record type,
subtype DATA_TYPE is std_logic_Vector(DATA_WIDTH-1 downto 0);
type MEM_WORD is
record
data : DATA_TYPE;
end record MEM_WORD;
type MEM_DATA_ARRAY_TYPE is array (natural range <>) of MEM_WORD;
Vivado Synthesis does not infer a Block RAM in the above example as it does not support memory model created using VHDL record type.
This issue is tentatively scheduled to be fixed in Vivado's 2013.2 build release.
The workaround would be to modify the HDL to avoid using a record type. Here is an example,
subtype DATA_TYPE is std_logic_Vector(DATA_WIDTH-1 downto 0);
type MEM_DATA_ARRAY_TYPE is array (natural range <>) of DATA_TYPE;