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AR# 52431

Virtex-7 FPGA GTH Transceivers, ACJTAG-IEEE 1149.6 - Use Mode in Engineering Sample (ES) Silicon


This answer record discusses the IEEE 1149.6 - ACJTAG use mode in the Virtex-7 FPGA GTH Initial ES and General ES silicon.


After configuration, it is required that the CPLL and QPLL input reference clocks be active and toggling, and the CPLL/QPLL are powered up (CPLLPD=1b0 and/or QPLLPD=1b0) prior to enabling ACJTAG.

This requirement only applies to the instantiated transceivers. For unconfigured devices or uninstantiated transceivers, there is no requirement.

AR# 52431
Date Created 10/17/2012
Last Updated 04/15/2013
Status Active
Type General Article
  • Virtex-7