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AR# 52431 Virtex-7 FPGA GTH Transceivers - ACJTAG Use Mode in Engineering Sample (ES) Silicon

Description

This answer record discusses the ACJTAG use mode in the Virtex-7 FPGA GTH Initial ES and General ES silicon.

Solution

After configuration,it is required that the CPLL andQPLL input reference clocks be activeand toggling, and the CPLL/QPLLare powered up (CPLLPD=1b0 and/or QPLLPD=1b0) prior to enabling ACJTAG.

This requirement only applies to the instantiated transceivers. For unconfigured devices or uninstantiated transceivers, there is no requirement.

Actions

AR# 52431
Date Created 10/17/2012
Last Updated 01/25/2013
Status Active
Type General Article
Devices
  • Virtex-7
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