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AR# 52447

7 Series Integrated Block for PCI Express - v1.7 userclk2 incorrectly constrained in XDC file when generating x8Gen2 core


Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

When generating the 7 Series Integrated Block for PCI Express v1.7 core, userclk2 is incorrectly constrained to 125 MHz instead of 250 MHz.


This is a known issue that isscheduled to be fixed in the next release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
10/23/2012 - Initial release

Linked Answer Records

Master Answer Records

AR# 52447
Date Created 10/23/2012
Last Updated 12/17/2012
Status Active
Type Known Issues
  • 7 Series Integrated Block for PCI Express (PCIe)