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AR# 52484

Virtex-6 Embedded TEMAC Wrapper - The RAMB36E1 address [15] should be tied High

Description

When using the Virtex-6 Embedded TEMAC Wrapper v1.6 and earlier, the modules rx_client_fifo_8/16.v/vhd and tx_client_fifo_8/16.v/vhd instantiate a RAMB36E1.

There are two address pins, ADDRARDADDR(15) and ADDRBWRADDR(15), connected to GND.

According to page 27 of the Memory User Guide (UG363), this is not allowed:

"For cascadable block RAM using the RAMB36E1, the data width is one bit, and the address bus is 16 bits [15:0]. 

The address bit 15 is only used in cascadable block RAM. For non-cascading block RAM, connect High."

Solution

In the design tool releases prior to and after ISE 13.4, the tools automatically correct this (tied address bit 15 to VCC even when RTL is connected to GND). 

ISE Design Suite 13.4 does not.

If using ISE Design Suite 13.4, ADDRARDADDR(15) and ADDRBWRADDR(15) should be connect High in the RTL.

Revision History
12/19/2012 - Initial release

AR# 52484
Date Created 12/19/2012
Last Updated 09/08/2014
Status Active
Type General Article
Tools
  • ISE Design Suite - 13.4
IP
  • Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper