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AR# 52493

LogiCORE IP Aurora 8B10B v8.3, ISE 14.3 - CRC failure in timing simulation using ISE generated Place and Route netlist

Description

If the ISE design tools generated Place and Route netlist is used, CRC failure is observed in timing simulation, and a TEST PASS and CRC FAIL message is issued by testbench that comes with Aurora 8B10B core.

Solution

CRC_PASS_FAIL_N and CRC_VALID signals are used to check valid CRC at the receive side of Aurora 8B10B core. The issue is that the CRC_PASS_FAIL_N signal is asserted before CRC_VALID is asserted.

The following changes need to be made in the simulation/<component name>_tb.v module. Note that #1 delay (in bold) is added into the always blocks.

always @ (posedge crc_pass_fail_n_1)
begin
#1;
if(flag_1 == 1)
begin
flag_2 <= 1'b1;
flag_1 <= 1'b0;
end
end

always @ (posedge crc_pass_fail_n_2)
begin
#1;
if(flag_3 == 1)
begin
flag_4 <= 1'b1;
flag_3 <= 1'b0;
end
end

Revision history:
10/30/2012 - Initial release

AR# 52493
Date Created 10/18/2012
Last Updated 10/31/2012
Status Active
Type General Article
IP
  • Aurora 8B/10B