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AR# 52497 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 (ISE 14.3) - Initial VF and Total VF value of 0 in a physical function is not allowed with SR-IOV enabled

Description

Version Found: v1.3
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

When configuring the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 core in CORE Generator, one can set SR-IOV Capability Structure Initial VF and Total VF to 0 in a physical function with SR-IOV enabled. This is not a supported use case.

Solution

This is a known issue and is scheduled to be fixed in a future release of the core. In the future release, the ability to set the value of 0 for Initial VF and Total VF, when SR-IOV is enabled, will be disabled.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
10/23/2012 - Initial Release

Actions

AR# 52497
Date Created 10/23/2012
Last Updated 10/23/2012
Status Active
Type
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
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