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AR# 52503 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 (ISE 14.3/2012.3) - How to access the core via DRP ports?

Description

Version Found: v1.3
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.3 Product Guide does not provide timing diagrams for accessing the core via DRP ports.

Solution

Accessing the core via DRP ports is currently not supported.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
10/23/2012 - Initial Release

Actions

AR# 52503
Date Created 10/23/2012
Last Updated 10/23/2012
Status Active
Type
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
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