Design Assistant

Zynq-7000 AP SoC Design Assistant

The Design Assistant will walk you through the recommended design flow forZynq-7000 AP SoCwhile debugging commonly encountered issues. The Design Assistant will not only provide useful design and troubleshooting information, but also point you to the exact documentation you need to read to help you design efficiently with Zynq-7000 AP SoC.

NOTE: This answer record is part of XilinxZynq-7000 APSoC Solution Center (Xilinx Answer 52512). XilinxZynq-7000 AP SoCSolution Center is available to address all questions related to Zynq-7000 AP SoC. Whether you are starting a new design withZynq-7000 AP SoCor troubleshooting a problem, use theZynq-7000 AP SoCSolution Center to guide you to the right information.

(Xilinx Answer 52538)Zynq-7000 AP SoC Boot and Configurationhelps you find all Zynq-7000 AP SoC answer records related to boot and configuration common questions or known issues

(Xilinx Answer 51779)Zynq-7000 AP SoC Example Designscontains useful hints to help with the HW design of your Zynq-7000 Programmable Logic (PL).

(Xilinx Answer 50863)Zynq-7000 AP SoC Debug keeps track of all the Zynq-7000 AP SoC answer records related to all the debug solutions available, including debug guides and how to setup third-party debugging tools.

(Xilinx Answer 52540)Zynq-7000 AP SoC FAQs helps you findall Zynq-7000 AP SoCfrequentlyasked questions.

(Xilinx Answer 52600)Zynq-7000 AP SoCStandaloneApplications Developmenthelps you find all Zynq-7000 AP SoC answer records related toStandalone common questions or known issues

(Xilinx Answer 52599)Zynq-7000 AP SoCOperating SystemsDevelopmenthelps you find all Zynq-7000 AP SoC answer records related toOS' common questions or known issues

Answer Number	Answer Title	Version Found	Version Resolved
52539	Zynq-7000 AP SoC - Board Design	N/A	N/A
52538	Zynq-7000 AP SoC - Boot and Configuration	N/A	N/A
52540	Zynq-7000 AP SoC - Frequently Asked Questions	N/A	N/A
51779	Zynq-7000 AP SoC Example Designs	N/A	N/A
50863	Zynq-7000 AP SoC - Debug	N/A	N/A
52599	Zynq-7000 AP SoC - Operating Systems Development	N/A	N/A
52600	Zynq-7000 AP SoC - Standalone Applications Development	N/A	N/A
53051	Zynq-7000 AP SoC - PS DDR Controller	N/A	N/A

Documentation

Zynq-7000 AP SoC - Documentation Summary

Zynq-7000 AP SoC Document Central: System, Device, Board, Kit, IP core, PL Design Tools, Application Notes, White Papers, Articles, and others.

NOTE: This answer record is part of Xilinx Zynq-7000 AP SoC Solution Center (Xilinx Answer 52512). Xilinx Zynq-7000 AP SoC Solution Center is available to address all questions related to Zynq-7000 AP SoC. Whether you are starting a new design with Zynq-7000 AP SoC or troubleshooting a problem, use the Zynq-7000 AP SoC Solution Center to guide you to the right information.

The documents are applicable to the family of Zynq-7000 AP SoC devices. After clicking on a link, select the desired document. Be sure to consider your device type, the document revision (generally use the latest) and/or the applicable design tool revision.

Resources

• Zynq-7000 AP SoC Solution Centers (Xilinx Answer 52512): Highest view of the Technical Support Landscape for Zynq-7000.
• Zynq-7000 AP SoC Design Assistants (Xilinx Answer 52511): Focus on specific technical areas.
• Zynq-7000 AP SoC Design Advisories (Xilinx Answer 47915): Device notification alert
• On-line Documents (xilinx.com/support/...): All Zynq-7000 Devices. Lists the User Guides (UG), Application Notes (XAPP), Errata (EN), and White Papers (WP).
• Xilinx Technical Support: Corporate Level.
• Xilinx Glossary of Technical Terms: Corporate Level.
• Zynq-7000 EPP rebranded Zynq-7000 AP SoC (All Programmable SoC) Announcement

Marketing Documents

• Overview (DS190): Product features and selection guide.
• XA Overview (DS188): Product features and selection guide for Automotive applications.
• Solutions for a Wide Range of Embedded Systems (WP369): System performance, flexibility, scalability and integration for developers. Optimized for power, cost and size.
• Next Generation 28 nm FPGA Technology (WP312): Combination high-performance, low-power process with architectural innovations.

Evaluation Board Documents

Xilinx Boards and Kits (Xilinx Answer 43746). Lists all boards and kits offered by Xilinx.

zc702 Board with 7z020 Device

• Evaluation Kit Website: Overview, Hardware, Tools and IP, Documents and Designs, Additional Resources
• Evaluation Kit Documentation Website: User Guides, Targeted Reference Designs, Example Designs and Board Files.

zc706 Board with 7z045 Device

• Evaluation Kit Website: Overview, Hardware, Tools and IP, Documents and Designs, Additional Resources
• Evaluation Kit Documentation Website: User Guides, Targeted Reference Designs, Example Designs and Board Files.

ZedBoard with 7z020 Device

• ZedBoard.org: Community-based website featuring Avnet/Digilent's development board based on Zynq-7000 7z020 device. 

Tutorials

• EDK/SDK (CTT) Concepts, Tools, Techniques (UG873): Create a design in ISE and run Hello World. Be sure to match CCT version with Design Suite tool version.

• Technical Reference Manaul (UG585): All Zynq-7000 devices. 1700+ page comprehensive User Guide with functional descriptions from system level content to register programming.

• Data Sheet for 7z010 and 7z020 (DS187): DC and AC Switching Characteristics.
• Data Sheet for 7z030 and 7z045 (DS191): DC and AC Switching Characteristics.

• Errata Sheets for 7z010 and 7z020 (EN208, EN210): DC and AC Switching Characteristics.
• Errata Sheets for 7z030 and 7z045 (EN220, EN228, EN229): DC and AC Switching Characteristics.

• Supplemental Device Document List (Xilinx Answer 52730) Items not yet included in the released Device Documents.

Programmable Logic (7 Series FPGAs Documents)

• XADC User Guide (UG480): Functional descriptions and register programming of the dual ADCs.
• SelectIO Resources (UG471): Technical reference to the SelectIO buffers.
• Clocking Resources (UG472): Technical reference to clocking resources.
• Memory Resources (UG473): Functional description as a Block RAM and FIFO.
• GTX Transceiver (UG476): Functional description of the GTX transceivers are applicable to the 7z030 and 7z045 devices.
• Integrated Block for PCIe (UG 477): Functional description and operation.
• Integrated Block for PCIe (DS821): Functional description.
• DSP48E1 Slice (UG478): Function description and configuration options.
• IP Core Release Notes and Known Issues (XTP025): Collection of IP core issues.
• DSP48E1 Cascade Signal Accessibility (Xilinx Answer 35690): Can the cascade signals be connected to PL logic?

IP Supplier and Industry Standard Documents

• IP Supplier and Industry Standard Documents (Xilinx Answer 47921): List of all the IP Supplier and Industry Standard documents related to the design of the Zynq-7000 device.

System Documents

• Technical Reference Manual (UG 585): All Zynq-7000 Devices. 1700+ page comprehensive User Guide with functional descriptions from system level content to register programming.
• Boot and Configuration Master AR (Xilinx Answer 52538):

Board Design Documents

• Packaging and Pinout Specification (UG865): All Zynq-7000 Devices. Device drawings, mechanical drawings, thermal specifications, package markings, solder pad guide.
• PCB Design and Pin Planning Guide (UG933): All Zynq-7000 Devices. Comprehensive PCB design guide. Bypass, trace impedance/lengths/termination, and design strategies.

• Heat Sink Weight Considerations (Xilinx Answer 12291): Guidelines when a bulky heatsink is required.

Application Notes

• HLS Designs in Vivado (XAPP745): Is IP cores to generate high-level synthesis controlled by the CPUs.
• TRD: Sobel filter using Vivado HLS (XAPP890): Implement a Sobel edge detection filter using the ZC702 board.
• High-performance Demonstration using Video (UG792) (link to v14.1, April 24, 2012): Implement a video DMAs to show throughput on AXI_HP ports and DDR memory on PS.
• Hardware in the Loop (HIL) Simulation (XAPP744): Method/solution to bring the CPUs within the ISE Design Suite Simulator (ISim).

Design Tool Documents

Note: ISE 14.1 or later Design ;Suite tools are required to create designs for Zynq-7000 AP SoC devices.

• Design Tools Release Notes ISE 14.1 (UG631): Design Tools Release Notes for ISE 14.1.
• (Xilinx Answer 47392)

EDK Resolved and Known Issues

ISE, PlanAhead and related implementation tools: ISE Design Suite documentation page

• Xilinx Command Line Tools User Guide (UG628)
• ChipScope Pro Software and Cores User Guide (UG029)
• PlanAhead Tutorial: Debugging with ChipScope (UG677)
• Xilinx Problem Solvers

Software Developement Documents

• Software Developer Guide (SDG) (UG821): For all Zynq-7000 AP SoC devices. Standalone/Linux, SMP/AMP, and other software topics.
• Open Source Linux Wiki: For all Zynq-7000 AP SoC devices.

OS and Libraries Document Collection (UG643)
The Linux drivers are provided via the Xilinx Open Source Wiki
Xilinx Alliance Program partners provide system software solutions for IP, middleware, operation systems, etc.

git Information Links:

• http://git-scm.com
• http://git-scm.com/documentation
• http://git-scm.com/download

EDK Documentation

The EDK documentation set can be accessed from the Embedded Development Kit (EDK) documentation page.

EDK Concepts, Tools, and Techniques (UG683)
Embedded System Tools Reference Manual (UG111)

OS and Libraries Document Collection (UG643)
Platform Specification Format Reference Manual (UG642)

XPS/EDK Supported IP Web Site
http://www.xilinx.com/ise/embedded/edk_ip.htm

EDK IP Derivative Device Family Support

Revision History
03/22/2013 - Updated to correct the application note links
11/20/2012 - Initial release

Answer Number	Answer Title	Version Found	Version Resolved
47921	Zynq-7000 AP SoC - IP Supplier and Industry Standard Document Summary	N/A	N/A
52730	Zynq-7000 AP SoC - Supplemental Device Documents List	N/A	N/A
52639	Zynq-7000 AP SoC, Registers - List of register updates for TRM.	N/A	N/A
12291	Packaging - What is the maximum weight limit (spring loading) for a particular package/heatsink combination?	N/A	N/A
47915	Design Advisory Master Answer Record for Zynq-7000 AP SoC Devices	N/A	N/A
43746	Xilinx Boards and Kits Solution Center - Documentation	N/A	N/A
35690	DSP48 Slice - Can the DSP48 slice cascades (ACIN, BCIN, PCIN, ACOUT, BCOUT, PCOUT) be connected to fabric?	N/A	N/A
47392	14.x EDK - Known Issues Master Answer Record	N/A	N/A

Design Advisories

Design Advisory Master Answer Record for Zynq-7000 AP SoC Devices

The Zynq-7000 devices are documented in the Zynq data sheet, technical reference manual and other documents. Important design advisories and other considerations that transcend these documents are listed here. The source point for technical content begins in the Xilinx Zynq-7000 AP SoC Solution Center (Xilinx Answer 52512).

Design Advisories Alerted on February 18, 2013

(Xilinx Answer 47916) Answer Records related to errata items: Zynq-7000 AP SoC Devices - Silicon Revision Differences
(Xilinx Answer 53450) Design Advisory for Zynq-7000 AP SoC, USB - ULPI interface requires input hold time of 1 ns
(Xilinx Answer 54190) Design Advisory for Zynq-7000 AP SoC, APU - L2 cache Operation Requires Programming of the slcr.L2C_RAM Register
(Xilinx Answer 54195) Design Advisory for Zynq-7000 VCCPLL Sensitivity

Answer Number	Answer Title	Version Found	Version Resolved
47916	Zynq-7000 AP SoC Devices - Silicon Revision Differences	N/A	N/A
53450	Design Advisory for Zynq-7000 AP SoC, USB - ULPI interface requires input hold time of 1 ns	N/A	N/A
54190	Design Advisory for Zynq-7000 AP SoC, APU - L2 cache Operation Requires Programming of the slcr.L2C_RAM Register	N/A	N/A

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