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AR# 5252

1.5i Alliance - Methods to reduce simulation time in VSS


Keywords: VSS, Synopsys, reduce, speed, ngm, -r

Urgency: Standard

General Description:

The following are general guidelines for reducing simulation
time when using the Synopsys VSS simulator.


1. Don't use the retain hierarchy (-r switch) when running
NGD2VHDL. This will create larger simulation netlists which
generally take longer to compile and simulate.

2. Don't correlate to original design (don't use the .ngm file
with NGDANNO). This can increase the runtime of NGDANNO.

3. With VSS, you have a choice to compile the libraries and/or
design with either an interpretive compile or a C compiler.
The C-compiler type of simulation is much faster, but it also requies a
C Compiler to be set up on the system as well as requiring a
different set of switches. The interpretive compile is slower
but adds further debugging features (i.e. allows you to look
into the code during simulation). Xilinx currently only
supports interpretive compiling because it is not machine
and compiler dependent. You have the option to use the
C-compiler to speed up simulation; however, you will have to
consult the Synopsys documentation to find out how to
appropriately setup VSS for your system.

4. Make sure the system has plenty of memory. As the devices get
larger, the netlists get larger and so do the memory

5. Use the command-line version of VSS, not the GUI. The
command-line version of VSS has less overhead than the GUI
version and is generally a bit faster.

AR# 5252
Date Created 08/31/2007
Last Updated 07/31/2001
Status Archive