This answer record contains information useful to PCB layout engineers using the Zynq-7000 AP SoC device family. This answer record includes information vital to successful layout of a Zynq-based PCB as well as information that will ease design and layout efforts.
NOTE: This answer record is part of the Xilinx Zynq-7000 AP SoC Solution Center (Xilinx Answer 52512). Xilinx Zynq-7000 AP SoC Solution Center is available to address all questions related to Zynq-7000 AP SoC. Whether you are starting a new design with Zynq-7000 AP SoC or troubleshooting a problem, use the Zynq-7000 AP SoC Solution Center to guide you to the right information.
Top Answer Records Related to Zynq-7000 AP SoC PCB Design
(Xilinx Answer 52847) Zynq-7000 - Board Design - Sequencing for SRST and POR Signals
(Xilinx Answer 47590) Zynq-7000 AP SoC, XADC - On-chip Voltage and Temperature References are not working
(Xilinx Answer 51996) Zynq-7000, DDRC - What are the Zynq Processing System DDR data sheet parameters?
(Xilinx Answer 52771) Zynq-7000 Power - Should MIO Bank 1 voltage selection be pulled High to Vcco_MIO0 or Vcco_MIO1?
(Xilinx Answer 12291) Packaging - What is the maximum weight limit (spring loading) for a particular package/heatsink combination?
(Xilinx Answer 5108) FPGA Configuration - What is the status of used I/O for Spartan/Virtex families during configuration?
(Xilinx Answer 3359) IBIS Simulation - What information do IBIS models provide? What is not provided?
Related Documentation
Zynq-7000 AP SoC Technical Reference Manual
Zynq-7000 AP SoC PCB Design and Pin Planning Guide
Zynq-7000 AP SoC (XC7Z010 and ZC7Z020) Data Sheet
Zynq-7000 AP SoC (XC7Z010 and ZC7Z020) Data Sheet
7-Series FPGA's GTX/GTH Transceivers User Guide
7-Series FPGA's XADC User Guide
Useful Links
VITA FMC Header Specification
IPC 2221A Generic Standard on Printed Board Design
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 52512 | Xilinx Zynq-7000 AP SoC Solution Center | N/A | N/A |
| 52511 | Zynq-7000 AP SoC Design Assistant | N/A | N/A |
| 53051 | Zynq-7000 AP SoC - PS DDR Controller | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 52847 | Zynq-7000 Board Design - Sequencing for SRST and POR Signals | N/A | N/A |
| 47590 | Zynq-7000 AP SoC, XADC - On-Chip Voltage References for ADCs are not accurate | N/A | N/A |
| 51996 | Zynq-7000, DDRC - What are the Zynq Processing System DDR data sheet parameters? | N/A | N/A |
| 52771 | Zynq-7000 Power - Should MIO Bank 1 voltage selection be pulled High to Vcco_MIO0 or Vcco_MIO1? | N/A | N/A |
| 12291 | Packaging - What is the maximum weight limit (spring loading) for a particular package/heatsink combination? | N/A | N/A |
| 5108 | FPGA Configuration - What is the status of used I/O for Spartan/Virtex families during configuration? | N/A | N/A |
| 3359 | IBIS Simulation - What information do IBIS models provide? What is not provided? | N/A | N/A |