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AR# 52626 7-Series - STARTUPE2_USRCCLK0 ignores first two clock cycles at output

Description

Applying a clock to USRCCLK0 using the STARTUPE2 primitive does not show any response on the external CCLK line for the first few cycles. Is this expected?

Solution

TheSTARTUPE2 primitive will ignore the first two clock cycles after configuration. However, stopping and starting the clock will not show this behavior after the clock is already in use.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35954 Virtex-5 - USERCLKO and CCLK not synchonised in STARTUP_VIRTEX5 when accessing SPI Flash N/A N/A

Actions

AR# 52626
Date Created 10/31/2012
Last Updated 02/25/2013
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
  • Artix-7
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