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AR# 52639

Zynq-7000 AP SoC, Registers - List of register updates for TRM.

Description

What are the pending updates for theregister descriptions that are not in the current TRM?

Solution

gem.phy_maint description, change 'pclk' to 'CPU_1x clock' (and all other places)
iic.Control_reg0[divisor_a], change 'pclk' to 'CPU_1x clock'
pl353.set_opmode[set_wr_bl] there is a typo: change NORE to NOR.
qspi.Rx_data_REG is8 bits wide
qspi.TX_thres_REG and RX_thres_REG:value is in 32-bit words. Themax supported value is 0x3F (0 to 63). Bitsare [5:0].
spi.Vendor Info should be Cadence SPI
spi.Config_reg0[7:6] change description to: Reserved, always write 00.
spi.Config_reg [8]:reserved
spi.Intr_status_reg0[0, 1, 6]: change type to W1C.
spi.Intrpt_{en, dis}_reg0[all]: writes: 0: no affect.
spi.Tx_data_reg0[TX_FIFO_data] valid bit field is 8-bit (7:0).
spi.Rx_data_reg0[RX_FIFO_data] valid bit field is 8-bit (7:0).
spi.TX_thres_reg0[DEPTH_of_TX_FIFO]: field size is [6:0], valid range is 1 to 127.
spi.RX_thres_reg0[DEPTH_of_RX_FIFO]: field size is [6:0], valid range is 1 to 127.
spi.Delay_reg0[all]: remove references to ext_clk.
spi.Intr_status_reg0[0, 1, 6] to WTC, not RO.
slcr.GPIOB_CTRL[VREF_SEL]: improve format.
New Register
Bit
Name
I/O
Description
slcr.FPGAx_THR_CNT
[LAST_CNT]
I
Clock pulse terminal count and software clock stop control. Any write to this register causes the clock to stop toggling. Use the [CPU_START] bit to start the clock for the number of pulses programmed into the [LAST_CNT] bit field:
0x0: Free-running clock (continuous clocking).
0x1 to 0x0FFFF: Number of clock pulses to generate (up to 65535 clock pulses).
The clock will toggle until the programmed number of pulses have been generated or is stopped by the rising edge of the FCLKCLKTRIGxN signal from the PL.
slcr.FPGAx_THR_CTRL
[CPU_START]
I
Start a clock (or restart a halted clock) by writing a 0 followed by a 1 to this bit (rising edge sensitive).
0: no effect on clock, but prepares for 0 to 1 transition.
1: start count or restart count if previous [CPU_START] value was 0.
A read will return the written value. The clock pulses continue until the [LAST_CNT] number of clocks occur or rising edge (logic 0 to logic 1) of the FCLKCLKTRIGxN signal is detected.
slcr.FPGAx_THR_CTRL
[CNT_RST]
I
Reset the pulse counter, readable using slcr.FPGAx_THR_STA [CURR_VAL]:
0: no effect
1: reset the pulse counter immediately if the clock generator is in the HALT state or reset the pulse counter when it enters the HALT state.
slcr.FPGAx_THR_STA
[CURR_VAL]
O
Current value of the pulse counter (i.e., the number of pulses that have already occurred), read-only. Only accurate when clock is stopped
slcr.FPGAx_THR_STA
[RUNNING]
O
Current running status of PL clock output, read-only:
0: Clock is stopped or in normal mode (OK to change throttle configuration).
1: Clock is running in debug mode (Do not change throttle configuration).
swdt.MODE[RSTLN], change 'clock cycles (pclk)' to 'CPU_1x clock cycles'
swdt.MODE[CLKSEL], change 'pclk' to 'CPU_1x clock' (multiple places)
ttc.Event_Register_{1:3}, change 'pclk' to 'CPU_1x'
ttc.Clock_Control_{1:3}[C_Src], change 'pclk' to 'CPU_1x clock'
ttc.Event_Control_Timer_{1:3}[E_Lo], change 'pclk' to 'CPU_1x clock'
ttc.Event_Register_{1:3}[Event], change 'pclk' to 'CPU_1x clock cycle'
uart.Modem_sts_reg0[DCTS]: Delta Clear To Send status. Write 1 to clear
Read: Indicates a change in state of the UART_CTSN input signal since this bit was last cleared.
0: No change has occurred since the last time this bit was cleared
1: Change of input state has occurred since the last time this bit was cleared
uart.Modem_sts_reg0[DDSR]: Delta Data Set Ready status. Write 1 to clear.
Read: Indicates a change in state of the UART_DSRN input signal since this bit was last cleared.
0: No change has occurred since the last time this bit was cleared
1: Change of input state has occurred since the last time this bit was cleared
uart.Modem_sts_reg0[TERI] Trailing Edge Ring Indicator status. Write 1 to clear.
Read:Indicates that the UART_RIN input signal has change from high to low state since this bit was last cleared.
0: No trailing edge has occurred since the last time this bit was cleared
1: Trailing edge has occurred since the last time this bit was cleared
uart.Modem_sts_reg0[DDCD] Delta Data Carrier Detect status. Write 1 to clear.
Read: Indicates a change in state of the UART_DCDN input signal since this bit was last cleared.
0: No change has occurred since the last time this bit was cleared
1: Change of input state has occurred since the last time this bit was cleared
uart.Chnl_int_sts_reg0[FRAME]: Receiver Framing Error interrupt status. This event is triggered whenever the receiver fails to detect a valid stop bit.
0 : No interrupt has occurred since this bit was last cleared
1 : An interrupt event has occurred since this bit was last cleared
uart.Chnl_int_sts_reg0[PARE]: Receiver Parity Error interrupt status. This event is triggered whenever the received parity bit does not match the expected value.
0 : No interrupt has occurred since this bit was last cleared
1 : An interrupt event has occurred since this bit was last cleared
uart.Chnl_int_sts_reg0[TIMEOUT]: Receiver Timeout Error interrupt status. This event is triggered whenever the receiver timeout counter has expired due to a long idle condition.
0 : No interrupt has occurred since this bit was last cleared
1 : An interrupt event has occurred since this bit was last cleared
uart.Chnl_int_sts_reg0[DMSI]: indicates a change of logic level on the DCD, DSR, RI or CTS modem flow control signals.
Update these uart.Channel_sts_reg0 descriptions (read-only).Register Prolog: This register returns the raw status of controllers dynamic conditions. The bits are not sticky and cannot be cleared or modified by software. These bits will change state due to the changing state of the controller, either by sequencing, I/O activity or changes affected by software.

RTRIG
RxFIFO level relative to uart.Rcvr_FIFO_trigger_level0[RTRIG], read-only:
0: less than Trigger Level
1: greater-than or equal Trigger Level

REMPTY

TACTIVE
Transmitter state, read-only:
0: inactive state, no
1: active state, controller is shifting out a character on TxD.

RACTIVE
Receiver state, read-only:
0: inactive state
1: active state, controller is shifting in a character from RxD.

FDELT:
Provides in channel statusRxFIFO level in comparison with the flow delay trigger level. [FDELT] is set whenever the FIFO level is greater than or equal to trigger level programmed in flow delay register.

TACTIVE.
Transmitter state machine active status. If in an active state, the transmitter is currently shifting out a character.
0 : Transmitter state machine is in an inactive state
1 : Transmitter state machine is in an active state

RACTIVE.
Receiver state machine active status. If in an active state, the receiver is has detected a start bit and is currently shifting in a character.
0 : Receiver state machine is in an inactive state
1 : Receiver state machine is in an active state

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52010 Zynq-7000 AP SoC - Documentation N/A N/A
AR# 52639
Date Created 11/26/2012
Last Updated 11/26/2012
Status Active
Type General Article
Devices
  • Zynq-7000