We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52657

Kintex-7 FPGA KC705 Evaluation Kit, Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform


The 7 Series Integrated Block for PCI Express core does not link up successfully on an Intel Z77 (Ivy Bridge) platform. This affects the out-of-box experience for customers wanting to use the Kintex-7 FPGA KC705 Evaluation Kit Base TRD.


This is a known issue for the core implemented in Artix and Kintex devices due to an Intel errata. To work around this issue, please refer to (Xilinx Answer 51135).

An out-of-the-box solution is available to enable customers to run the Kintex-7 FPGA KC705 Base TRD. This involves using a particular set of files (.bit and .mcs file) when running the Base TRD. The files needed, k7_pcie_dma_ddr3_base_x4_gen2.bit and KC705.mcs, can be found at the end of this answer record. Please make your selection based on your software version.

For information on how to run the Kintex-7 FPGA KC705 Base TRD, see the Kintex-7 FPGA Base Targeted Reference Design User Guide (UG882):

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45934 Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 52657
Date Created 10/31/2012
Last Updated 03/25/2013
Status Active
Type General Article
Boards & Kits
  • Kintex-7 FPGA KC705 Evaluation Kit