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AR# 52688

AXI Bridge for PCI Express v1.04.a - Completion TLP not generated when configured as Root Complex on Zynq devices


Version Found: v1.04.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

When AXI Bridge for PCI Express v1.04.a core is configured as x4Gen2 Root Port with 128-bit data width, it does not send the CplD TLP in response to a read from the endpoint even after receiving the valid data from AXI side.


This is a known issue to be fixed in the next release of the core.

NOTE: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 52688
Date Created 10/31/2012
Last Updated 08/26/2013
Status Active
Type Known Issues
  • AXI PCI Express (PCIe)