Version Found: v1.04.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)
When AXI Bridge for PCI Express v1.04.a core is configured as x4Gen2 Root Port with 128-bit data width, it does not send the CplD TLP in response to a read from the endpoint even after receiving the valid data from AXI side.
This is a known issue to be fixed in the next release of the core.
NOTE: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.