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AR# 52716

Design Advisory for Spartan-6 FPGAs - Configuration Readback including SEM_IP or POST_CRC causes power distribution network noise affecting SelectIO and GTP interfaces

Description

Any operation invoking readback of the configuration memory cell, such as the SEU Mitigation (SEM) IP or the built-in post-configuration CRC checking (POST_CRC), might affect SelectIO or GTP operation due to noise on the power distribution network (PDN), regardless of configuration interface (ICAP/SelectMap/JTAG). This issue is limited exclusively to Spartan-6 devices and does not affect all designs. Guidance is provided on how to determine if a design is prone to this issue.

Effect on GTP
PDN noise near GTP causes period change on rising edges of REFCLK, which causes period changes in GTP PLL outputs.

Effect on SelectIO
PDN noise will induce I/O jitter due to variations on VCCINT that cause an increase or decrease in circuit delays near the I/Os. All memory controller banks are impacted.  SelectIO are impacted in bank 0 (top), bank 2 (bottom), and banks 3 and 4 (left).

There is no effect on Global Clock Buffers.

Solution

How do I determine if my design needs to account for this issue?

Designs with the following characteristics are more vulnerable to being impacted.

1) GTP Interfaces
Designs using GTP interfaces.

2) SelectIO Interfaces
Designs using MCB.  SelectIO interfaces located in bank 0, 2, 3, or 4 that are running at higher than 300 Mb/s (3.3 ns) but have less than 500 ps of link margin.

What steps can I take to mitigate the problem if it affects my design?

SelectIO Interface Speed GTP Interface Readback Feature used Next Steps
300 Mbps (3.3ns) with less than 500ps of link margin, or any MCB No POST_CRC Update to SEM IP v3.4 or later. Scanning of GT rows is disabled by default. As your design has no GTP, in the core generation setup you can enable "Top GT Row" and "Bottom GT Row" scanning in the "Enable Scanning of GT Row(s)" section.
Any Yes POST_CRC Update to SEM IP v3.4 or later. See (Xilinx Answer 55276) for additional guidance. Scanning of GT rows is disabled by default. If your design does not use GTP in both the top and bottom of the device, you can enable scanning on rows that do not contain GTP. To do this in the core generation setup, enable "Top GT Row" or "Bottom GT Row" in the "Enable Scanning of GT Row(s)" section. Choose the options appropriate to the location of GTPs in your design.
300 Mbps (3.3ns) with less than 500ps of link margin, or any MCB
No SEM IP v3.3 or earlier Update to SEM IP v3.4 or later. Scanning of GT rows is disabled by default. As your design has no GTP, in the core generation setup you can enable "Top GT Row" and "Bottom GT Row" scanning in the "Enable Scanning of GT Row(s)" section.
Any Yes SEM IP v3.3 or earlier Update to SEM IP v3.4 or later. See (Xilinx Answer 55276) for additional guidance. Scanning of GT rows is disabled by default. If your design does not use GTP, in both the top and bottom of the device you can enable scanning on rows that do not contain GTP. To do this in the core generation setup, enable "Top GT Row" or "Bottom GT Row" in the "Enable Scanning of GT Row(s)" section. Choose the options appropriate to the location of GTPs in your design.


When will the SEM IP v3.4 or later be available?

The Pre-production SEM IP v3.4 is available in ISE Design Suite 14.4. The production SEM IP v3.5 with beam testing completed is available in ISE Design Suite 14.5.  Newer versions of the SEM IP are also available in ISE Design Suite 14.6 and ISE Design Suite 14.7.

Do I lose any SEU coverage by adopting SEM IP v3.4 or later?

If the new mode to skip configuration memory rows including GTP is used, there is a reduction in SEU coverage.

Device Total Rows per Device Coverage Reduction for 1 Row Coverage Reduction for 2 Rows
6SLX25T 5 15.70% Not Applicable
6SLX45T 8 6.75% Not Applicable
6SLX75T 12 5.05% 11.1%
6SLX100T 12 5.90% 11.8%
6SLX150T 12 6.55% 13.1%

Note: the coverage reduction is less than the number of coverage rows divided by total rows because configuration rows containing GTP blocks have substantially fewer configuration bits.  

Note: When skipping the bottom GT row, SEM IP v3.5 or later should be used. See (Xilinx Answer 55276)

Four real design examples are also implemented with essential bits and used bits considered. The table below indicates that the real loss of coverage may be considerably less.

Device LUT Utilization Total Essential Bits Essential bits disabled in row Essential bits percentage reduction in coverage
6SLX25T 35% 1,138,559 13,372 1.2%
6SLX45T 20% 1,236,695 14,574 1.2%
6SLX45T 35% 2,452,973 14,531 0.6%
6SLX100T 60% 8,607,723 258,967 3.0%

For more information on Essential Bits, see (Xilinx Answer 41199) and (Xilinx Answer 41197).

To obtain SEU detection coverage for your design, contact your local FAE, or open a WebCase with Xilinx Technical Support.

Is my IOSTANDARD a consideration?

The IOSTANDARD setting does not have a positive or negative impact.

Is there any performance impact of the new SEM IP?

SEM IP v3.4 or later will take about three to four times longer to perform initialization and full device scan.

If you require further assistance on this issue, open a WebCase with Xilinx Technical Support.

Linked Answer Records

Associated Answer Records

AR# 52716
Date Created 11/15/2012
Last Updated 03/13/2015
Status Active
Type Design Advisory
Devices
  • Spartan-6
IP
  • Soft Error Mitigation