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AR# 52780

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.4, 7 Series GTX Transceivers - Update needed to target Production Silicon

Description

The Ethernet 1000BASE-X PCS/PMA or SGMII v11.4 core targets 7 series GTX General ES Silicon. If targeting 7 series GTX Production Silicon devices, updates are needed to use the 7 series FPGAs Transceiver wizard v2.2. More information on the changes can be found at (Xilinx Answer 50617) and (Xilinx Answer 52844).

Solution

To update to the v2.3 GTX Transceiver wrapper files, follow these steps:

  1. Open the CORE Generator or Vivado tool interface.
  2. Go to IP catalog -> FPGA Features and Design -> IO interfaces -> 7 Series FPGAs Transceivers wizard v2.3
  3. Change component name to <component_name>_GTWIZARD.
  4. Choose protocol template as:
    Gigabit Ethernet CC -> if 1000basex or sgmiiwithout elastic buffer
    Gigabit Ethernet noCC -> in case of SGMII with elastic buffer
  5. Select optional ports TXPOWERDOWN,RXPOWERDOWN while generating the core.
  6. Copy and replace the corresponding files in the transceiver folder in the gigabit core example design folder:
    <component_name>_gtwizard_rx_startup_fsm.v[hd] (replaces <component_name>_rx_startup_fsm.v[hd])
    <component_name>_gtwizard_tx_startup_fsm.v[hd] (replaces <component_name>_tx_startup_fsm.v[hd])
    <component_name>_gtwizard_recclk_monitor.v[hd]
    <component_name>_gtwizard_init.v[hd]
  7. a. Copy <component_name>_gtwizard_gt.v[hd] from the work area.
    b. Connect TXPD_IN[0] to TXELECIDLE pin on instance of gtxe2.
  8. a. Copy <component_name>_gtwizard.v[hd] from the work area.
    b. Rename the instance name of <component_name>_gtwizard_gt to gt0_GTWIZARD_i to prevent constraint failure.
  9. Modifications to <component_name>_gtwizard_init.v[vhd]:
    a. Comment out Dynamic Reconfiguration (DRP) port signals (valid only for GTX).
    b. Comment out Receive Ports - RX Decision Feedback Equalizer(DFE) port signals.
    c. Comment out declaration and instantiation of <component_name>_GTWIZARD_ADAPT_TOP_DFE and <component_name>_GTWIZARD_ADAPT_TOP_LPM (Valid only for GTX).
    d. Modify STABLE_CLOCK_PERIOD according the period of independent_clock. In this design set it to 5.
    e. Define signals gt0_gtrxreset_gt and gt0_gttxreset_gt as follows:

    VHDL
    gt0_gttxreset_gt <= gt0_gttxreset_t or GT0_GTTXRESET_IN;
    gt0_gtrxreset_gt <= gt0_gtrxreset_t or GT0_GTRXRESET_IN;

    VERILOG
    assign gt0_gttxreset_gt = gt0_gttxreset_t || GT0_GTTXRESET_IN;
    assign gt0_gtrxreset_gt = gt0_gtrxreset_t || GT0_GTRXRESET_IN;

    f. Map GT0_GTRXRESET_IN and GT0_GTTXRESET_IN with gt0_gtrxreset_gt and gt0_gttxreset_gt respectively.
    g. Keep DRP output signals on <component_name>_GTWIZARD_i as open and tie input DRP signals to '0's (valid only for GTX).
    h. Map gt0_rxdfeagchold_i to PORT RXDFEAGCHOLD of instance gt0_rxresetfsm_i (valid only for GTX).
    i. A BUFG needs to be added between GT0_RXOUTCLK_OUT port of core_GTWIZARD_i and RX_REC_CLK0 port of gt0_rx_recclk_mon_i.
  10. Modifications to <component_name>_transceiver.v[hd]:
    a. Connect independent_clock to GT0_CPLLLOCKDETCLK_IN instead of tying to '1'.
    b. Add ports on gtwizard_inst instance:
    i. GT0_GTREFCLK0_COMMON_IN. Connect it to gtrefclk.
    ii. GT0_QPLLLOCK_OUT: Keep this open.
    iii. GT0_QPLLLOCKDETCLK_IN: independent_clock.
    iv. GT0_QPLLRESET_IN: connect this to '0'.
    c. Modify:
    VHDL
    modify gt_reset_rx <= not cplllock or (rxreset and resetdone_rx); in the case of SGMII with fabric elastic buffer to
    gt_reset_rx <= (rxreset and resetdone_rx);
    modify gt_reset_rx <= not cplllock or (rxreset_int and resetdone_rx); for all other cases to
    gt_reset_rx <= (rxreset_int and resetdone_rx);
    modify gt_reset_tx <= not cplllock or (txreset_int and resetdone_tx); to
    gt_reset_tx <= (txreset_int and resetdone_tx)
    modify rxpowerdown_int <= rxpowerdown_reg & rxpowerdown; in the case of SGMII with fabric elastic buffer to
    rxpowerdown_int <= rxpowerdown_reg & rxpowerdown_reg;

    VERILOG
    Modify assign gt_reset_rx = !cplllock || (rxreset & resetdone_rx); in the case of SGMII with fabric elastic buffer to
    assign gt_reset_rx = (rxreset & resetdone_rx);
    Modify assign gt_reset_rx = !cplllock || (rxreset_int & resetdone_rx); for all other cases to
    assign gt_reset_rx = (rxreset_int & resetdone_rx);
    Modify assign gt_reset_tx = !cplllock || (txreset_int & resetdone_tx); to
    assign gt_reset_tx = (txreset_int & resetdone_tx);
    Modify assign rxpowerdown_int = {2{rxpowerdown}}; in the case of SGMII with fabric elastic buffer to
    assign rxpowerdown_int = {2{rxpowerdown_reg}};

NOTE: Take care of hierarchy and instance names according to your implementation.

7 series GTX Production Silicon will be targeted in the v11.5 wizard scheduled to be released in the ISE 14.4/Vivado 2012.4 design tools.

AR# 52780
Date Created 11/05/2012
Last Updated 12/06/2012
Status Active
Type General Article
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII