UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 52841

14.2 ChipScope IBERT - Virtex-7 - GTH - Wrong setting for QPLL_REFCLK_DIV

Description

When using IBERT for Virtex-7 GTH, QPLL_REFCLK_DIV is set incorrectly for QUAD 116 only.

With line rate=10.3125 and refclk =312.5M, it is set incorrectly to 1.

Solution

This parameter can be changed manually to '0' in the IBERT console.

This will be fixed in a future version of IBERT.
AR# 52841
Date Created 11/14/2012
Last Updated 12/18/2014
Status Active
Type General Article
Devices
  • Virtex-7
Tools
  • ChipScope Pro - 14