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AR# 52941

Zynq-7000 AP SoC Base Targeted Reference Design - Release Notes and Known Issues Master Answer Record

Description

This is the Release Note and Known Issues Master Answer Record for the Zynq-7000 AP SoC Base Targeted Reference Design.

Solution

The Zynq-7000 AP SoC Base TRD is developed on the Zynq-7000 AP SoC ZC702 Evaluation Kit. 

The primary components of the TRD are:

Processing System (PS):

  • Dual ARM Cortex-A9 core
  • ARM AMBA AXI interconnect
  • Multi-protocol, 32-bit DDR DRAM controller
  • 1 GB DDR3 running at 533 MHz
  • USB, Ethernet, UART, I2C, SD MMC, GPIO

Programmable Logic (PL):

  • 2 AXI interconnects, 64-bit wide at 150 MHz
  • 1 AXI interconnect, 32-bit wide at 75 MHz
  • AXI VDMA(s)
  • HD video input and output interface
  • Sobel accelerator
  • 2 AXI performance monitors

 

Hardware Test Setup Requirements

The prerequisites required to run and test the Base TRD are:

  • Zynq-7000 AP SoC ZC702 Evaluation Kit with XC7Z020 CLG484-1 EPP, Rev C or above
  • HDMI-to-HDMI or HDMI-to-DVI cable
  • Monitor capable of supporting 1080p60
  • USB Type-A Female to USB Micro-B Male cable
  • USB hub
  • USB mouse
  • USB keyboard
  • ISE Design Suite, Embedded Edition v14.1 or later
  • Installation of required license files for the TRD

 

Zynq-7000 AP SoC Base TRD v1.0 for ISE 14.1 with GES Silicon

  • Silicon
    • The Zynq-7000 AP SoC ZC702 Evaluation Kit ships with GES silicon. Refer to GES Errata for any further information
  • IP
    • LogiCORE IP Processing System 7 (processing_system7) : v4.00.a
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
    • LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.01.a
    • LogiCORE IP AXI Interconnect (axi_interconnect) : v1.06.a
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v1.00.a
    • LogiCORE IP Video Timing Controller (axi_vtc) : v3.00.a
    • AXI Internal Test Pattern Generator (axi_tpg) : v2.00.a
    • Compact Video Controller (logicvc) : v2.04.a
    • External video signal from Imageon FMC (fmc_imageon_hdmi_in) : v1.03.a
    • DVI2AXI (dvi2axi) : v3.01.a
    • sobel_filter_top: v1.01.a
    • sobel_strm32 : v1.00.a
    • clk_detect : v1.00.a
    • RGB to YCBCR converter (rgb2ycbcr422) : v1.00.a
    • YCBCR to RGB converter (ycbcr4222rgb) : v1.00.a
    • Video Multiplexer (vsrc_sel) : v1.00.a
    • Utility Reduced Logic (util_reduced_logic) : v1.00.a
    • Utility Flip-Flop (util_flipflop) : v1.10.a
    • clock_generator : v4.03.a
  • Known Issues
    • On bootup, on the UART console (teraterm / hyperterminal) connected to the PC, the Linux shell prompt will not appear until the graphical Qt application has exited. 
      This is because in the Linux init script, the Qt-based Graphical application is launched as the last step in the boot-up. 
      If the Linux prompt on UART is desired on bootup, please edit the "init.sh" file on the SD card and remove / comment out the line that runs the following:
      "./run_sobel.sh -qt".
    • QMetaObject::connectSlotsByName: No matching signal for on_tpgColorBar_pressed() appears periodically tty ttyPS0 console. 
      Known issue, please ignore.


Zynq-7000 AP SoC Base TRD v2.0 for ISE 14.2 (2012.2) with GES Silicon

  • Silicon
    • The Zynq-7000 AP SoC ZC702 Evaluation Kit ships with GES silicon.  Refer to GES Errata for any further information
  • IP
    • LogiCORE IP Processing System 7 (processing_system7) : v4.01.a
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
    • LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.02.a
    • LogiCORE IP AXI Interconnect (axi_interconnect) : v1.06.a
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v2.00.a
    • LogiCORE IP Video Timing Controller (axi_vtc) : 
    • AXI Internal Test Pattern Generator (axi_tpg) : v2.00.a
    • Compact Video Controller (logicvc) : v2.05.c (supports yuv output)
    • External video signal from Imageon FMC (fmc_imageon_hdmi_in) : v1.03.a
    • DVI2AXI (dvi2axi) : v3.02.a (supports SOF on tuser)
    • sobel_filter_top: v1.02.a (interrupt based)
    • clk_detect : v1.00 a
    • Video Multiplexer (vsrc_sel) : v1.00.a
    • Utility Reduced Logic (util_reduced_logic) : v1.00.a
    • Utility Flip-Flop (util_flipflop) : v1.10.a
    • clock_generator : v4.03.a
    • LogiCORE IP Chroma Resampler (v_cresample) : v3.00.a
    • LogiCORE IP Video Timing Controller (v_tc) : v5.00.a
    • LogiCORE IP YCrCb to RGB Color-Space Converter (v_ycrcb2rgb) : v6.00.a
    • ycbcr2rgb replaced by v_cresample and v_ycrcb2rgb (AXI interface EDK pcores)
    • rgb2ycbcr422 is removed as logicvc v2.05.a gives YCbCr 422 output
    • axi_tpg is configured to give YCrCb 422 video output
  • Known Issues
    • While generating (building) hardware bitstream, a message window will pop-up, saying there are 3 critical warning messages. 
      Please ignore these warnings and press OK, to continue with the bitstream generation.
    • When QT application starts "automatically", typing any command in the Zynq command shell (command area on top of QT application) does not work. 
      To fix this issue, exit the application and re-start the application
      [ ./run_sobel.sh -qt]


Zynq-7000 AP SoC Base TRD v3.0 for ISE 14.3 (2012.3) with GES Silicon

  • Silicon
    • The Zynq-7000 AP SoC ZC702 Evaluation Kit ships with GES silicon.  Refer to GES Errata for any further information
  • IP
    • LogiCORE IP Processing System 7 (processing_system7) : v4.01.a
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
    • LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.02.a
    • LogiCORE IP AXI Interconnect (axi_interconnect) : v1.06.a
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v2.00.a
    • AXI Internal Test Pattern Generator (axi_tpg) : v2.00.c
    • Compact Video Controller (logicvc) : v2.05.c
    • External video signal from Imageon FMC (fmc_imageon_hdmi_in) : v1.03.a
    • DVI2AXI (dvi2axi) : v3.02.a
    • sobel_filter_top : v1.02.a
    • clk_detect : v1.00.a
    • Video Multiplexer (vsrc_sel) : v1.00.a
    • Utility Reduced Logic (util_reduced_logic ) : v1.00.a
    • Utility Flip-Flop (util_flipflop) : v1.10.a
    • clock_generator : v4.03.a
    • LogiCORE IP Chroma Resampler (v_cresample) : v3.00.a
    • LogiCORE IP Video Timing Controller (v_tc) : v5.00.a
    • LogiCORE IP YCrCb to RGB Color-Space Converter (v
  • Known Issues
    • Warnings: While generating (building) hardware bitstream, a message window will appear, saying that there are 7 critical warning messages. 
      Please ignore these warnings and press OK, to continue with the bitstream generation.
      *** CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'ps7_0_PORB_pin_IBUF' at site B5, Site location is not valid
      *** CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'ps7_0_PS_SRSTB_pin_IBUF' at site C9, Site location is not valid
      *** CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'ps7_0_CLK_pin_IBUF' at site F7, Site location is not valid
      *** CRITICAL WARNING: [Constraints 18-11] Could not find cell or net 'VTC_0/*U_VIDEO_CTRL*/*SYNC2PROCCLK_I*/data_sync_reg[0]*'
      *** CRITICAL WARNING: [Constraints 18-11] Could not find cell or net 'VTC_0/*U_VIDEO_CTRL*/*SYNC2VIDCLK_I*/data_sync_reg[0]*'
      *** CRITICAL WARNING: [Constraints 18-329] No definition for group 'VTC_0_async_clock_conv_FFDEST', timing constraint is ignored
      *** CRITICAL WARNING: [Constraints 18-329] No definition for group 'VTC_0_vid_async_clock_conv_FFDEST', timing constraint is ignored


Zynq-7000 AP SoC Base TRD v4.0 for ISE 14.4 (2012.4) with GES Silicon

  • Silicon
    • The Zynq-7000 AP SoC ZC702 Evaluation Kit ships with GES Silicon.  Refer to GES Errata for any further information
  • IP
    • LogiCORE IP Processing System 7 (processing_system7) : v4.02.a
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
    • LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.04.a
    • LogiCORE IP AXI Interconnect (axi_interconnect) : v1.06.a
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v3.00.a
    • Compact Video Controller (logicvc) : v3.00.a
    • External video signal from Imageon (fmc_imageon_hdmi_in) : v1.03.a
    • sobel_filter_top : v1.04.a
    • clk_detect : v1.00.a
    • Video Multiplexer (vsrc_sel) : v1.00.a
    • Utility Reduced Logic (util_reduced_logic) : v1.00.a
    • Utility Flip-Flop (util_flipflop) : v1.10.a
    • clock_generator : v4.03.a
    • LogiCORE IP Chroma Resampler (v_cresample) : v3.01.a
    • LogiCORE IP Video Timing Controller (v_tc) : v5.01.a
    • LogiCORE IP YCrCb to RGB Color-Space Converter (v_ycrcb2rgb) : v6.01.a
    • LogiCORE IP Test Pattern Generator (v_tpg) : v4.00.a
    • LogiCORE IP Video In to AXI4-Stream (v_vid_in_axi4s) : v2.01.a
  • Known Issues
    • Warnings: While generating (building) hardware bitstream, a message window will pop-up, saying there are 5 critical warning messages. 
      Please ignore these warnings and press OK, to continue with the bitstream generation.
      *** CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'ps7_0_PS_PORB_pin_IBUF' at site B5, Site location is not valid
      *** CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'ps7_0_PS_SRSTB_pin_IBUF' at site C9, Site location is not valid
      *** CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'ps7_0_PS_CLK_pin_IBUF' at site F7, Site location is not valid
      *** CRITICAL WARNING: [Timing 38-124] The 'DATAPATHONLY' keyword is not supported [*/system_vtc_0_wrapper.ncf:2]
      *** CRITICAL WARNING: [Timing 38-124] The 'DATAPATHONLY' keyword is not supported [*/system_vtc_0_wrapper.ncf:4]


Zynq-7000 AP SoC Base TRD v5.0 for ISE 14.5 with Production Silicon

  • Silicon
    • The Zynq-7000 AP SoC ZC702 Evaluation Kit ships with Production Silicon.
  • IP
    • LogiCORE IP Processing System 7 (processing_system7) : v4.03.a
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
    • LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.04.a
    • LogiCORE IP AXI Interconnect (axi_interconnect) : v.1.06.a
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v.3.00.a
    • LogiCORE IP AXI4-Stream Video Remapper (axis_vremapper) : v1.00.a
    • Compact Video Controller (logicvc) : v3.00.a
    • External video signal from Imageon (fmc_imageon_hdmi_in) : v1.03.a
    • sobel_filter_top : v1.05.a
    • Video Multiplexer (vsrc_sel) : v1.00.a
    • Utility Reduced Logic (util_reduced_logic) : v1.00.a
    • Utility Flip-Flop (util_flipflop) : v1.10.a
    • Utility Vector Logic (util_vector_logic) : v1.00.a
    • clock_generator : v4.03.a
    • LogiCORE IP Chroma Resampler (v_cresample) : v3.01.a
    • LogiCORE IP Video Timing Controller (v_tc) : v5.01.a
    • LogiCORE IP YCrCb to RGB Color_Space Converter (v_ycrcb2rgb) : v6.01.a
    • LogiCORE IP Test Pattern Generator (v_tpg) : v4.00.a
    • LogiCORE IP Video In to AXI4-Stream (v_vid_in_axi4s) : v2.01.a
 Zynq-7000 AP SoC Base TRD v2.6.0 for Vivado 2013.2 with Production Silicon
 
  • Silicon
    • The Zynq-7000 AP SoC ZC702 Evaluation Kit ships with Production Silicon.
  •  IP
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v5.0
    • LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v6.0
    • LogiCORE IP AXI Interconnect (axi_interconnect) : v2.0
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v4.0
    • Compact Video Controller (logicvc) : v3.01.a
    • External video signal from Imageon (fmc_imageon_hdmi_in) : v2.01.a
    • sobel_filter : v1.0
    • Video Multiplexer (vsrc_sel) : v1.0
    • Utility Reduced Logic (util_reduced_logic) : v1.0
    • Utility Flip-Flop (util_flipflop) : v1.0
    • Utility Vector Logic (util_vector_logic) : v1.0
    • LogiCORE IP Clocking Wizard (clock_generator) : v5.0
    • LogiCORE IP Chroma Resampler (v_cresample) : v4.0
    • LogiCORE IP Video Timing Controller (v_tc) : v6.0
    • LogiCORE IP YCrCb to RGB Color_Space Converter (v_ycrcb2rgb) : v7.0
    • LogiCORE IP Test Pattern Generator (v_tpg) : v5.0
    • LogiCORE IP Video In to AXI4-Stream (v_vid_in_axi4s) : v3.0

 
 Zynq-7000 AP SoC Base TRD v2.7.0 for Vivado 2013.3 with Production Silicon
 
  • Silicon
    • The Zynq-7000 AP SoC ZC702 Evaluation Kit ships with Production Silicon
  • IP
    • LogiCORE IP Processing System 7 (processing_system7) : v5.3
    • LogiCORE IP Processor System Rest Module (proc_sys_reset) : v5.0
    • LogiCORE IP AXI Interconnect (axi_interconnect) : v2.1
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v5.0
    • Compact Video Controller (logicvc) : v3.01.a
    • External video signal from Imageon (fmc_imageon_hdmi_in) : v2.01.a
    • sobel_filter : v1.0
    • Video Multiplexer (vsrc_sel) : v1.0
    • Utility Reduced Logic (util_reduced_logic) : v1.0
    • Utility Flip-Flop (util_flipflop) : v1.0
    • LogiCORE IP Clocking Wizard clk_wiz : v5.1
    • LogiCORE IP Chroma Resampler (v_cresample) : v4.0
    • LogiCORE IP Video Timing Controller (v_tc) : v6.0
    • LogiCORE IP Test Pattern Generator (v_tpg) : v5.0
    • LogiCORE IP Video In to AXI4-Stream (v_vid_in_axi4s) : v3.0

Zynq-7000 AP SoC Base TRD v2.8.0 for Vivado 2013.4 with Production Silicon

  • Silicon
    • The Zynq-7000 AP SoC ZC702 Evaluation Kit ships with Production Silicon
  • IP
    • LogiCORE IP Processing System 7 (processing_system7) : v5.3
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v5.0
    • LogiCORE IP AXI Video DIrect Memory Access (axi_vdma) : v6.1
    • LogiCORE IP AXI Interconnect (axi_interconnect) : v2.1
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v5.0
    • Compact Video Controller (logicvc) : v3.01.a
    • External video signal from Imageon (fmc_imageon_hdmi_in) : v2.01.a
    • sobel_filter : v1.0
    • Video Multiplexer (vsrc_sel) : v1.0
    • Utility Reduced Logic (util_reduced_logic) : v1.0
    • Utility Flip-Flop (util_flipflop) : v1.0
    • Utility Vector Logic (util_vector_logic) : v1.0
    • LogiCORE IP Clocking Wizard (clk_wiz) : v5.1
    • LogiCORE IP Chroma Resampler (v_cresample) : v4.0
    • LogiCORE IP Video Timing Controller (v_tc) : v6.1
    • LogiCORE IP YCrCb to RGb Color_Space Converter (v_ycrcb2rgb) : v7.1
    • LogiCORE IP Test Pattern Generator (v_tpg) : v5.0
    • LogiCORE IP Video In to AXI4-Stream (v_vid_in_axi4s) : v3.0
  There is no Zynq-7000 AP SoC Base TRD release for Vivado 2014.1
 
  Zynq-7000 AP SoC Base TRD v2.9.0 for Vivado 2014.2 with Production Silicon

 

  • Silicon
    • The Zynq-7000 AP SoC ZC702 Evaluation Kit ships with Production Silicon
  • IP
    • LogiCORE IP Processing System 7 (processing_system7) : v5.4
    • LogiCORE IP Processor System Reset Module (proc_sys_reset) : v5.0
    • LogiCORE IP AXI Video DIrect Memory Access (axi_vdma) : v6.2
    • LogiCORE IP AXI Interconnect (axi_interconnect) : v2.1
    • LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v5.0
    • Compact Video Controller (logicvc) : v4.00.a
    • External video signal from Imageon (fmc_imageon_hdmi_in) : v2.0
    • image_filter : v1.0
    • Timing Multiplexer (vtiming_mux) : v1.0
    • LogiCORE IP Clocking Wizard (clk_wiz) : v5.1
    • LogiCORE IP Video Timing Controller (v_tc) : v6.1
    • LogiCORE IP Test Pattern Generator (v_tpg) : v5.0
    • LogiCORE IP Video In to AXI4-Stream (v_vid_in_axi4s) : v3.0
  • Known Issues
    • (Xilinx Answer 59731) - Zynq-7000 AP SoC ZC702 Evaluation Kit - 2013.4 Base TRD - Monitor may not synch-up
    • In TPG selection, when the bounding box touches the boundary of the monitor there is a horizontal line which appears on the monitor.
    • Occasionally, on some hardware set-ups, ADV7611 I2C Slave returns NACK for I2C transaction. adv7611 12-004c: not an adv7611 on address 0x98.
      The workaround is to reboot the system
    • VDMA driver shows error when video options changed. xilinx-vdma 40090000.axivdma: Channel deadfe50 has errors 8000, cdr 0 tdr 0. 
      However, this has no functional impact.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47864 Zynq-7000 AP SoC ZC702 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
59731 Zynq-7000 AP SoC ZC702 Evaluation Kit - 2013.4 Base TRD - Monitor may not synch-up N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
59731 Zynq-7000 AP SoC ZC702 Evaluation Kit - 2013.4 Base TRD - Monitor may not synch-up N/A N/A
AR# 52941
Date Created 11/15/2012
Last Updated 01/12/2015
Status Active
Type Known Issues
Boards & Kits
  • Zynq-7000 All Programmable SoC ZC702 Evaluation Kit