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AR# 52953

AXI VDMA - What clock crossing constraints do I need to add for this core?

Description

There are a number of clocks and interfaces in this core (and I am in asynchronous mode so some interfaces have different clocks than other interfaces). I can see that when in EDK, the TCL is writing some constraints for me, but not all CDCpaths are covered by constraints. What are the correct constraints for these paths? Which ones can I safely conclude are false paths and apply TIGs to?

Solution

In XPS, the TCL for the core writes clock crossing TIGconstraints for certain flip-flop instances that are known to be false paths. However, the AXIVDMA coreuses theFIFO Generator coreon the back end for its asynchronous buffers. FIFO Generator does not supply constraints for its clock crossing paths and the AXI VDMA does not have the ability to safely constrain clock crossing paths inside this core without making some dangerous assumptions (See AR 46044). Therefore, those paths are left unconstrained and the user must constrain those paths based on the clock topology of their design.

Therefore, if you receive errors such as this which are CDC paths inside the FIFO, you can safely TIG them.

--------------------------------------------------------------------------------
Slack: -2.620ns (requirement - (data path - clock path skew + uncertainty))
Source: axi_vdma_out/axi_vdma_out/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_CH1_FTCH_Q_IF.GEN_CH1_QUEUE.FTCH_QUEUE_I/GEN_FIFO_FOR_ASYNC.I_CH1_FTCH_FIFO/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1 (FF)
Destination: axi_vdma_out/axi_vdma_out/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_CH1_FTCH_Q_IF.GEN_CH1_QUEUE.FTCH_QUEUE_I/GEN_FIFO_FOR_ASYNC.I_CH1_FTCH_FIFO/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_1 (FF)
Requirement: 0.205ns
Data Path Delay: 0.685ns (Levels of Logic = 0)(Component delays alone exceeds constraint)
Clock Path Skew: -1.097ns (3.519 - 4.616)
Source Clock: clk148 rising at 639.795ns
Destination Clock: Internal_BRAM_port_a_BRAM_Clk rising at 640.000ns
Clock Uncertainty: 1.043ns

Clock Uncertainty: 1.043ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.388ns
Phase Error (PE): 0.845ns

Maximum Data Path at Slow Process Corner: axi_vdma_out/axi_vdma_out/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_CH1_FTCH_Q_IF.GEN_CH1_QUEUE.FTCH_QUEUE_I/GEN_FIFO_FOR_ASYNC.I_CH1_FTCH_FIFO/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1 to axi_vdma_out/axi_vdma_out/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_CH1_FTCH_Q_IF.GEN_CH1_QUEUE.FTCH_QUEUE_I/GEN_FIFO_FOR_ASYNC.I_CH1_FTCH_FIFO/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X27Y1.AMUX Tshcko 0.422 axi_vdma_out/axi_vdma_out/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_CH1_FTCH_Q_IF.GEN_CH1_QUEUE.FTCH_QUEUE_I/GEN_FIFO_FOR_ASYNC.I_CH1_FTCH_FIFO/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_q<0><3>
axi_vdma_out/axi_vdma_out/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_CH1_FTCH_Q_IF.GEN_CH1_QUEUE.FTCH_QUEUE_I/GEN_FIFO_FOR_ASYNC.I_CH1_FTCH_FIFO/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1
SLICE_X24Y1.BX net (fanout=1) 0.248 axi_vdma_out/axi_vdma_out/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_CH1_FTCH_Q_IF.GEN_CH1_QUEUE.FTCH_QUEUE_I/GEN_FIFO_FOR_ASYNC.I_CH1_FTCH_FIFO/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_q<0><1>
SLICE_X24Y1.CLK Tdick 0.015 axi_vdma_out/axi_vdma_out/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_CH1_FTCH_Q_IF.GEN_CH1_QUEUE.FTCH_QUEUE_I/GEN_FIFO_FOR_ASYNC.I_CH1_FTCH_FIFO/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_q<1><3>
axi_vdma_out/axi_vdma_out/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_CH1_FTCH_Q_IF.GEN_CH1_QUEUE.FTCH_QUEUE_I/GEN_FIFO_FOR_ASYNC.I_CH1_FTCH_FIFO/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_1
------------------------------------------------- ---------------------------
Total 0.685ns (0.437ns logic, 0.248ns route)
(63.8% logic, 36.2% route)
--------------------------------------------------------------------------------


The recommendation is to apply the normal from-to TIGs between asynchronous clock domain groups.

You may also see unconstrained asynchronous reset paths going from the AXI VDMA's reset module to the reset pins on theFIFO. This path is synchronized inside the FIFO Generator core and is thus a false path. It can be safely TIG'd. Here is an example of what this path might look like in the timing report:


--------------------------------------------------------------------------------

Slack: -3.657ns (requirement - (data path - clock path skew + uncertainty))
Source: axi_vdma_master/axi_vdma_master/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I/GENERATE_LEVEL_P_S_CDC_NO_RST.s_level_out_d2 (FF)
Destination: axi_vdma_master/axi_vdma_master/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_ASYNC_FIFO_FLUSH_SOF/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg (FF)
Requirement: 0.020ns
Data Path Delay: 3.093ns (Levels of Logic = 1)(Component delays alone exceeds constraint)
Clock Path Skew: -0.147ns (2.569 - 2.716)
Source Clock: Output_Video_Clk rising at 459.980ns
Destination Clock: clk_200_0000MHzMMCM0 rising at 460.000ns
Clock Uncertainty: 0.437ns

Clock Uncertainty: 0.437ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.143ns
Phase Error (PE): 0.356ns

Maximum Data Path at Slow Process Corner: axi_vdma_master/axi_vdma_master/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I/GENERATE_LEVEL_P_S_CDC_NO_RST.s_level_out_d2 to axi_vdma_master/axi_vdma_master/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_ASYNC_FIFO_FLUSH_SOF/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X21Y71.AQ Tcko 0.337 axi_vdma_master/axi_vdma_master/GEN_SPRT_FOR_S2MM.S2MM_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF_CDC_I/GENERATE_PULSE_CDC_S_P.s_pulse_out_s_h_d1_cdc_to
axi_vdma_master/axi_vdma_master/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_RESET_FOR_ASYNC.AXIS_RESET_CDC_I/GENERATE_LEVEL_P_S_CDC_NO_RST.s_level_out_d2
SLICE_X8Y48.D4 net (fanout=40) 1.403 axi_vdma_master/axi_vdma_master/I_RST_MODULE/GEN_RESET_FOR_S2MM.sig_s2mm_axis_resetn
SLICE_X8Y48.DMUX Tilo 0.218 axi_vdma_master/axi_vdma_master/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.I_MSTR_SKID_FLUSH_SOF/sig_reset_reg
axi_vdma_master/axi_vdma_master/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/s_axis_fifo_ainit1
SLICE_X7Y42.SR net (fanout=34) 0.714 axi_vdma_master/axi_vdma_master/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/s_axis_fifo_ainit
SLICE_X7Y42.CLK Trck 0.421 axi_vdma_master/axi_vdma_master/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_ASYNC_FIFO_FLUSH_SOF/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg
axi_vdma_master/axi_vdma_master/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_ASYNC_FIFO_FLUSH_SOF/I_ASYNC_FIFOGEN_FIFO/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg
------------------------------------------------- ---------------------------
Total 3.093ns (0.976ns logic, 2.117ns route)
(31.6% logic, 68.4% route)

--------------------------------------------------------------------------------


We are currently investigating the ability to apply core-level constraints using XDC in Vivado Design Suite so that clock crossing paths in FIFO Generator can be correctlyconstrained by the AXIVDMA.

Also, note thatthe user is responsible for all CDCconstraints when using this core fromCORE Generator.

AR# 52953
Date Created 11/30/2012
Last Updated 11/30/2012
Status Active
Type General Article
IP
  • Video DMA