52968

Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

If simulating the 7 series Integrated Block for PCI Express v1.7 in Cadence IES, the tool results in the following warning message:

ncelab: *W,CSINFI (/user/nak/work/pcie_7x_v1_4_x4/pcigen1_x4/pcigen1_x4/pcigen1_x4.srcs/sources_1/ip/pcie_7x_v1_7_0/pcie_7x_v1_7_0/example_design/xilinx_pcie_2_1_ep_7x.v,531|63): implicit wire has no fanin (board.EP.init_pattern_bus).
ncelab: *W,CSINFI: implicit wire has no fanin ({*Name Protected*}).
ncelab: *W,CSINFI: implicit wire has no fanin ({*Name Protected*}).
ncelab: *W,CSINFI: implicit wire has no fanin ({*Name Protected*}).

It is safe to ignore these waring messages. It will be fixed in the next release of the core.

NOTE: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
11/20/2012 - Initial release

AR# 52968
Date Created	11/20/2012
Last Updated	11/20/2012
Status	Active
Type
Devices	Virtex-7
Tools	Vivado - 2012.3
IP	7 Series Integrated Block for PCI Express (PCIe)

AR# 52968 7 Series Integrated Block for PCI Express v1.7 (Vivado 2012.3) - Simulation warning in Cadence IES "ncelab: W,?CSINFI: implicit wire has no fanin ({Name Protected*})"

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AR# 52968 7 Series Integrated Block for PCI Express v1.7 (Vivado 2012.3) - Simulation warning in Cadence IES "ncelab: *W,?CSINFI: implicit wire has no fanin ({*Name Protected*})"

Description

Solution

Actions

AR# 52968 7 Series Integrated Block for PCI Express v1.7 (Vivado 2012.3) - Simulation warning in Cadence IES "ncelab: W,?CSINFI: implicit wire has no fanin ({Name Protected*})"