If there are only a few nets unrouted, it might be possible to route the net manually from FPGA Editor.
In this case, the associated net is a clock signal from a BUFGMUX component.
The design is failing routing in ISE 14.x but has passed in 13.x.
If manual routing does not provide any solution to the problem then an alternative is to use the same placement in 1SE 14.x as was working in ISE 13.x for the BUFGMUX in the design.
Check the location of these components with FPGA Editor in ISE 13.x and use the corresponding constraints: