We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 53009

AXI 7series DDRx 1.06a - Can read modify write cycle be avoided when ECC is enabled and full write burst is provide?


My axi_7series_ddrx IP is configured with data width set to 72-bit and ECC enabled.

When working 4 Kbyte transactions, a full write burst is provided to the AXI4 interface.

However, the memory controller still performs Read-Modify-Write (RMW) cycles. 

Why does this happen?


When ECC and AXI interface are enabled, RMW cycles cannot be avoid.

AXI allows writes strobed on a per beat basis. 

The axi_7series_ddrx IP does not know in advance that all write strobes will be asserted and as a result has no ability to remove the RMW cycles. 

AR# 53009
Date Created 11/19/2012
Last Updated 10/15/2014
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Zynq-7000
  • ISE Design Suite - 14.3
  • Vivado Design Suite - 2012.3