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AR# 53023

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 (Vivado 2012.4) - "WARNING: [Vivado 12-180] No cells matched / CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object."

Description

Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

When implementing the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 core by selecting performance level as 'Extreme'
in Gen1/Gen2 core configuration, the tool gives the following warnings:

WARNING: [Vivado 12-180] No cells matched 'core_i/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk*.CPL_FIFO_16KB.U0/
SPEED_250MHz.RAMB36E1[2].u_fifo'.
[../run/example_project/core_example/core_example.srcs/constrs_1/imports/example_design/
xilinx_pcie_3_0_7vx_ep_1_lane_gen1_xc7vx330t-ffg1157-1-PCIE_X0Y1.xdc:146]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object.
[../run/example_project/core_example/core_example.srcs/constrs_1/imports/example_design/
xilinx_pcie_3_0_7vx_ep_1_lane_gen1_xc7vx330t-ffg1157-1-PCIE_X0Y1.xdc:146]
WARNING: [Vivado 12-180] No cells matched 'core_i/inst/pcie_top_i/pcie_7vx_i/pcie_bram_7vx_i/cpl_fifo/genblk*.CPL_FIFO_16KB.U0/
SPEED_250MHz.RAMB36E1[3].u_fifo'.
[../run/example_project/core_example/core_example.srcs/constrs_1/imports/example_design
/xilinx_pcie_3_0_7vx_ep_1_lane_gen1_xc7vx330t-ffg1157-1-PCIE_X0Y1.xdc:147]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object.
[../run/example_project/core_example/core_example.srcs/constrs_1/imports/example_design/
xilinx_pcie_3_0_7vx_ep_1_lane_gen1_xc7vx330t-ffg1157-1-PCIE_X0Y1.xdc:147]

Solution

This is a known issue to be fixed in a future release of the core. As a work-around, please select 'Good' in Performance Level for 'BRAM Configurations Options' in the core configuration GUI.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
12/18/2012 - Initial release

AR# 53023
Date Created 12/17/2012
Last Updated 08/26/2013
Status Active
Type General Article
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)