UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 53028

2012.x Vivado - "ERROR: [Common 17-39] 'launch_xsim' failed due to earlier errors"

Description

I have a design in the Vivado tool which I want to run a behavioral simulation with different parameters. For this task, I have created some simulation runs with different names as follows:

  • "sim1 model_PCIe"
  • "sim2"
  • "sim3(model_GTX)"

However, when I attempt to run the simulation, the following error appears:

"ERROR: [Common 17-39] 'launch_xsim' failed due to earlier errors"

Why does this occur?

Solution

This is a known issue that occurs in Vivado when a simulation run that contains blank or empty spaces in the name is executed.

In this case, for the run "sim1 model_PCIe"

To avoid this problem, remove the spaces as follows: "sim1_model_PCIe".

This issue is fixed in the Vivado 2013.1 tool.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
53030 2012.x Vivado - "ERROR: [Common 17-69] Command failed: Failed to compile the design!" N/A N/A
AR# 53028
Date Created 11/20/2012
Last Updated 04/05/2013
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite