The -.100ns limit is an arbitrary tool limitation that is not currently planned to be changed. However, consider checking the board design against the board guidelines in the Zynq-7000 PCB Design and Pin Planning Guide (UG933), as large negative values are not expected when the guidelines are followed.
The suggested work-around is to set the value to -.100ns.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 53051 | Zynq-7000 AP SoC - PS DDR Controller | N/A | N/A |