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AR# 53039

14.3 EDK, Zynq-7000 DDRC - Why is the PS7 DDR Configuration limit DQS to Clock delay to -.100ns/0ns?


Why is the PS7 DDR Configuration limit DQS to Clock delay to -.100ns/0ns?

What if my calculation is more negative?


The -.100ns/0ns limit is an arbitrary tool limitation. 

However, consider checking the board design against the board guidelines in the Zynq-7000 PCB Design and Pin Planning Guide (UG933), as large negative values are not expected when the guidelines are followed.

To work around this, set the value to the lowest possible number and enable training, if available. 

The 0ns requirement has recently been added to better match routing constraints of MIG (Memory Interface Generator) board design requirements of the PL.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
53051 Zynq-7000 AP SoC - PS DDR Controller N/A N/A
AR# 53039
Date Created 11/20/2012
Last Updated 04/23/2014
Status Active
Type General Article
  • Zynq-7000
  • EDK - 14.4
  • EDK - 14.3
  • EDK - 14.2
  • EDK - 14.1