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AR# 53051

Zynq-7000 AP SoC - PS DDR Controller

Description

This answer record collects Zynq-7000 AP SoC answer records related to the Processing System (PS) DDR Controller (DDRC), including common questions and known issues.

Note: This answer record is part of Xilinx Zynq-7000 AP SoC Solution Center (Xilinx Answer 52512).
Xilinx Zynq-7000 AP SoC Solution Center is available to address all questions related to Zynq-7000 AP SoC.
Whether you are starting a new design with Zynq-7000 AP SoC or troubleshooting a problem, use the Zynq-7000 AP SoC Solution Center to guide you to the right information.

Solution

Top Issues on DDR Board Design
 
(Xilinx Answer 51996)  Zynq-7000, DDRC - What are the Zynq Processing System DDR data sheet parameters?
(Xilinx Answer 46871)  14.2 EDK, Zynq-7000 - Which IBIS models should be used for Zynq devices?
(Xilinx Answer 51778)  Zynq-7000 - How should the PS DDR3 CKE signal be terminated?
(Xilinx Answer 46723)  Zynq-7000 AP SoC - Can I swap PS DDR DQ pins for board design?
(Xilinx Answer 52539)  Zynq-7000 AP SoC - Board Design Article

Top Issues on DDR Configuration and Training
 
(Xilinx Answer 46778)  Zynq-7000 - How do I configure the PS DDRC board parameters?
(Xilinx Answer 59836)  Zynq-7000 SoC - How does the DDRC training work?
(Xilinx Answer 54398)  Zynq-7000 AP SOC - When using a faster DDR device than the clock frequency, which timing specifications can be used?
(Xilinx Answer 51790)  Zynq-7000 - How is the DDRC address mapping used?
(Xilinx Answer 53039)  14.3 EDK, Zynq-7000 DDRC - Why is the PS7 DDR Configuration limit DQS to Clock delay to -.100ns?

Top Issues on DDR Debug
 
(Xilinx Answer 60454)  Design Advisory Zynq-7000 PS DDR Controller - DDR IO's are not properly configured in ISE/EDK and Vivado 2013.3 and earlier
(Xilinx Answer 62042)  Zynq-7000 AP SoC, Vivado 2014.2 - PS DDRC asserts ODT during reads
(Xilinx Answer 51074) 14.2 EDK, Zynq-7000 - PS DDRC with ECC does not function
(Xilinx Answer 47516)  Zynq-7000 AP SoC, DDR - Controller Mishandles STREX Instruction
(Xilinx Answer 47484)  Zynq-7000 AP SoC, AXI - Deadlock Can Occur when OCM and DDR are Accessed by AXI_HP Article
(Xilinx Answer 47514)  Zynq-7000 AP SoC, DDR - DDR3 Starts DRAM Clock too Early after Exiting Self-Refresh

Related Documentation

Zynq-7000 AP SOC Technical Reference Manual:
Chapter 10: DDR Memory Controller

Zynq-7000 All Programmable SoC PCB Design and Pin Planning Guide

Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020) Data Sheet: DC and AC Switching Characteristics

Zynq-7000 All Programmable SoC (XC7Z030 and XC7Z045) Data Sheet: DC and AC Switching Characteristics

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52511 Zynq-7000 AP SoC Design Assistant N/A N/A

Child Answer Records

AR# 53051
Date Created 11/26/2012
Last Updated 11/17/2014
Status Active
Type Solution Center
Devices
  • Zynq-7000