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AR# 53056 7 Series Integrated Block for PCI Express v1.7 - "ERROR:Xst:2927 - Source file ../source/PCIe_portion_pipe_clock_tandem.vhd" does not exist"

Description


Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

When generating the 7 Series Integrated Block for PCI Express v1.7 core by selecting VHDL, XST results in the following error:

"ERROR:Xst:2927 - Source file ../source/PCIe_portion_pipe_clock_tandem.vhd" does not exist
ERROR:Xst:2927 - Source file ../source/PCIe_portion_tandem_cpler.vhd does not exist"

Solution


Tandem configuration support is available only for Verilog for now. Please select 'Verilog' when generating the core.

This issue will be fixed in a future release of the core.

NOTE: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
11/26/2012 - Initial release

Actions

AR# 53056
Date Created 11/26/2012
Last Updated 11/26/2012
Status Active
Type
IP
  • 7 Series Integrated Block for PCI Express (PCIe)
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