The AXI TFT controller supports configuration of a Chrontel CH-7310 chip through the IIC interface.
The IIC interface automatically configures the default values to the Chrontel chip immediately after reset de-assertion.
While AXI TFT is configuring the Chrontel chip, a write to the CCR register over AXI affects the already pending IIC transactions.
How can I resolve this issue?
This is a limitation of the AXI_TFT core.
To work around this issue, the following two precautions need to be taken:
1. Wait for 10 us after reset before writing to the CCR register (BASEADDR+0x0000000C).
2. Before each write into the CCR register, ensure any previous writes to CCR have executed by polling the 31st bit for a value of 0.
This issue is fixed in Vivado 2013.3.