In PCS loopback mode, if there is no connection from TXP/TXN to RXP/RXN, then RXRECCLK output from CDR is not expected to be good.
This is due to a lack of data transitions at the input to lock to.
If a design requires RXRECCLK for its fabric logic, the design can fail.
For these designs, it is recommended to use CDR in "lock to reference" mode.
Follow the steps below to make sure that the CDR is in "lock to reference" mode:
Step1: Drive the following signals
Step2: Perform a full RX reset of the transceiver
If a design does not use RXRECCLK for fabric logic, only Step 2 is required.
12/18/2012 - Initial release