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AR# 53118

2012.3 Vivado HLS - How can the message: "@W [SCHED-21] Estimated clock period exceeds the target" be explained and worked around?

Description

There are a few situations where this message can occur; following are two examples taken from the matrix multiplication examples:

Example 1:

Pipeline with II=1 is used in the design.

@W [SCHED-21] Estimated clock period (7.67ns) exceeds the target (target clock period: 5ns, clock uncertainty: 0ns, effective delay budget: 5ns).
@W [SCHED-21] The critical path consists of the following:
 'load' operation ('o_z_im_temp_V_load') on local variable 'o_z_im_temp.V' (0 ns)
 'select' operation ('o_z_im_temp.V', matrix_test.cpp:42) (0.71 ns)
 'shl' operation ('lhs.V', matrix_test.cpp:47) (0 ns)
 'add' operation ('r.V', matrix_test.cpp:47) (2.9 ns)
 'icmp' operation ('r', matrix_test.cpp:47) (1.28 ns)
 'or' operation ('brmerge_i_i1', matrix_test.cpp:47) (0.71 ns)
 'and' operation ('qb', matrix_test.cpp:47) (0.71 ns)
 'add' operation ('__Val2__', matrix_test.cpp:47) (1.36 ns)

Example 2:

@W [SCHED-21] Estimated clock period (12.8ns) exceeds the target (target clock period: 10ns, clock uncertainty: 0ns, effective delay budget: 10ns).
@W [SCHED-21] The critical path consists of the following:
        'load' operation ('M_load_2', top.cpp:36) on array 'M' (2.39 ns)
        'partselect' operation ('__Val2__', top.cpp:37) (0 ns)
        'shl' operation ('lhs.V', top.cpp:37) (0 ns)
        'sub' operation ('__Val2__', top.cpp:37) (3.13 ns)
        'icmp' operation ('r', top.cpp:37) (1.41 ns)
        'or' operation ('brmerge_i_i3', top.cpp:37) (0.71 ns)
        'and' operation ('qb', top.cpp:37) (0.71 ns)
        'add' operation ('__Val2__', top.cpp:37) (2.11 ns)
        'bitconcatenate' operation ('M_imag_V_addr_25960_part_set', top.cpp:37) (0 ns)
        'store' operation (top.cpp:37) of variable 'M_imag_V_addr_25960_part_set' on array 'M' (2.39 ns)

the line 37 is M[i][j].imag -= line_M [k].real*line_L [k].imag  + line_M [k].imag*line_L [k].real;

Solution

In both examples, the warning message shows that one path does not meet timing. It also shows the operations in the critical path.

In more detail, in Vivado HLS, there are some rules that the tool must obey in terms of dependency for arranging the operations; this is call scheduling.

The interpretation of the warning is that too many operations are scheduled to happen in one clock cycle and the tool cannot split it automatically with the current code and constraints/directives provided.

There is a tutorial available and a section on matrix multiplication that the user is advised to refer to:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug871-vivado-high-level-synthesis-tutorial.pdf

Regarding the above examples, there are different solutions as follows:

Example 1:

You can set the initialization interval (II) of the pipeline to 2, thus, allowing more flexibility for the VHLS tool to adjust each clock cycle to do the pipeline, but this changes the overall latency and throughput.

Example 2:

The critical path seen is the accumulator loop: loop k times around the expression "M[i][j].imag -= the_value" -> load the matrix value M[i][j], sub / add, store back the result.

A temporary variable could be used but if the tools do not do it, it is probably because it thinks the k value could be forced to have only one loop.

A change in the code to use a temporary variable creates a different scheduling which results in a better timing that meets the timing requirements.

AR# 53118
Date Created 11/26/2012
Last Updated 04/25/2013
Status Active
Type General Article
Tools
  • Vivado Design Suite