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AR# 53245

Vivado: a netlist generated for timing simulation looks to be the UNISIM-based netlist


After implementation, running "write_verilog -mode timesim" writes out a Verilog netlist used for timing simulation.

However, it is based on UNISIM components.

Why is this the case as the SIMPRIM library is referenced in timing simulation?


In Vivado, Verilog SIMPRIM and UNISIM library components are replaced by a single UNISIM component set with additional blocks specifically for timing annotation.

This is enabled by `ifdef XIL_TIMING in the UNISIM source code.

SIMPRIMS_VER is the logical library name to which the Verilog SIMPRIM is mapped.

In ISE, the SIMPRIM library components have separate names (with prefix X_ ) to the UNISIM components.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58882 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Behavioral Simulation N/A N/A
AR# 53245
Date 12/16/2014
Status Active
Type General Article
  • Vivado Design Suite