Version Found: v1.8
Version Resolved and other Known Issues: See
(Xilinx Answer 40469)When implementing a design with the 7 Series Integrated Block for PCI Express - v1.8 core, the tool reports the following setup timing violation:
Slack (VIOLATED) : -0.268ns
Source: core_i/inst/inst/pcie_top_i/pcie_7x_i/pcie_block_i/USERCLK
(rising edge-triggered cell PCIE_2_1 clocked by userclk1 {rise@0.000ns fall@1.000ns period=2.000ns})
Destination: core_i/inst/inst/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_sdp.ramb36sdp/genblk3_0.bram36_dp_bl.bram36_tdp_bl/DIBDI[8]
(rising edge-triggered cell RAMB36E1 clocked by userclk1 {rise@0.000ns fall@1.000ns period=2.000ns})
Path Group: userclk1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.000ns
Data Path Delay: 2.127ns (logic 1.040ns (48.900%) route 1.087ns (51.100%))
Logic Levels: 0
Clock Path Skew: -0.082ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.797ns = ( 6.797 - 2.000 )
Source Clock Delay (SCD): 5.240ns
Clock Pessimism Removal (CPR): 0.361ns
Clock Uncertainty: 0.059ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.095ns
Phase Error (PE): 0.000ns