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AR# 53290

Partial Reconfiguration - 7 series device layout of tiles (CLB, DSP, BRAM, INT) and a shared clocking structure of vertical clock spines between interconnect (routing) tiles


If implementing a Partial Reconfiguration design on a 7 series or Zynq-7000 device, the following errors might be encountered:

[XCad 248] Partition Name </top/reconfig_red> with Area Group <AG_reconfig_red> has a right edge that terminates on an improper column boundary at tile INT_L_X48Y50.
[XCad 252] This is due to Range SLICE_X0Y50:SLICE_X79Y99

This error is due to requirements of clock routing in these devices. The floorplan must be structured to include interconnect (INT) tiles so that clock routes have all the necessary resources to be completely created. Interconnect tiles are structured back-to-back (horizontally) and must not be split when creating the reconfigurable area group. The granularity required cannot be visualized in the PlanAhead tool, but the messages can be used to guide you to the appropriate size and resources in your reconfigurable partition. Use this feedback to adjust the width and contents in your area group ranges.


There are two changes that might be necessary to clear these issues with the floorplan.

The first change to make when encountering these errors is to ensure that all necessary reconfigurable resource types are included in the PR region: CLB, BRAM, DSP and INT resource types must be accounted for. The way to achieve this is to add this area group property to the reconfigurable partition in question:


This will automatically include all four resource types in the reconfigurable partition, thereby including all interconnect sites within this region. Note that this will include block RAM and DSP resource types even if you have not explicitly specified a range for them; all block RAM and DSP elements within the main CLB area group range will be included.

If after making that change you still encounter these errors, this means the left or right boundary of the CLB area group range splits interconnect tiles and must be adjusted slightly. The message (XCad 248) shows whether the left or right edge must be altered. Using the floorplan view in PlanAhead tool, adjust the width of the region by one CLB column. For certain devices, this means that the left-most or right-most CLB column cannot be included in the Reconfigurable Partition.

AR# 53290
Date Created 02/27/2013
Last Updated 09/06/2013
Status Active
Type General Article
  • Kintex-7
  • Virtex-7
  • Zynq-7000
  • Artix-7
  • PlanAhead - 14