UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 53299

MIG 7 Series - MIG fails during synthesis if System Clock = No Buffer and Reference Clock = Use System Clock

Description

Version Found: v1.7
Version Resolved: See (Xilinx Answer 45195)

Designs generated using MIG 7 Series with the settings" System Clock = No Buffer" and "Reference Clock = Use System Clock" fail during synthesis with the following messages:

ERROR:HDLCompiler:69 - "......\mig_7series_v1_6\user_design\rtl\mig_7series_v1_7.vhd" Line 960: <clk_ref_p> is not declared.
ERROR:HDLCompiler:69 - ".......\mig_7series_v1_6\user_design\rtl\mig_7series_v1_7.vhd" Line 961: <clk_ref_n> is not declared.
ERROR:HDLCompiler:854 - ".......\mig_7series_v1_6\user_design\rtl\mig_7series_v1_7.vhd" Line 496: Unit <arch_mig_7series_v1_6> ignored due to previous errors.

Solution

This is expected behavior when "System Clock = No Buffer" and "Reference Clock = Use System Clock" are chosen.

MIG will generate a design without I/O or buffers for the System Clock and Reference Clock.

If the System and Reference Clocks are not manually declared, Synthesis will fail because the mig_7series_v1_7_iodelay_ctrl module needs the reference clocks to be supplied.

If selecting "System Clock = No Buffer" and "Reference Clock = Use System Clock" is required, then you must declare the sys_clk_p/n and clk_ref_p/n signals in the mig_7series_v1_7 module.

Starting with MIG 1.9, this information will be added to the 7 Series FPGAs Memory Interface Solutions User Guide (UG586).

AR# 53299
Date Created 12/12/2012
Last Updated 08/13/2014
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series