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AR# 53319

ISE 14.x - XST - Can 14.2 XST handle writing of different data to the same address under different conditions with reference to a memory description?

Description

In the case of a memory description inan HDLcode where different datais writtento the same address under different conditions, 14.2 XSTis not able to handle this particular situation and results in incorrect logic.

Solution

Here is an example of a HDL code depicting the above explained scenario:

if rising_edge( clk ) then

if (rst) then
mem(addr) <='0';
else
mem(addr) <= data;
end if;
end if;

In the above description of the HDL code,different data is written to the same address under different conditions. Here "0"and "data" are written to the same address "addr" under different conditions(rst high and rst low),14.2 XST does not support this type of data handling and results in incorrect logic. This issue has been fixed in 14.4 XST with a flag/switch option. For XST to support the above behavior, the following lines need to be added to the .scr/.xst file before the run command:

OPTION:1

set -checkcmdline no
set -merge_ram_enables 1

Please ignore the following bogus warning messages that would appear in the synthesis report file, which is unrelated to the fix:

WARNING:Xst:15 - skipping parameter : merge_ram_enables
WARNING:Xst:1363 - Option "-merge_ram_enables" is not available for command set.

OPTION:2

To remove the above mentioned warnings, the following actions have been taken:

  • 14.5 XST has fixed he XST code to get rid of the second warning message which is as follows:

WARNING:Xst:1363 - Option "-merge_ram_enables" is not available for command set.

  • To get rid of the first warning message, append the following switch to the run command as the last line within the .scr/.xst file replacing the "set -merge_ram_enables 1" option that was originally provided,

-merge_ram_enables 1

The .scr/.xst will look like the following:

set -checkcmdline no
run
...
...
-merge_ram_enables 1

There will not be any difference in the functionality when using either of the two options, except that in the last option the warning messages will be cleared.

AR# 53319
Date Created 12/14/2012
Last Updated 02/19/2013
Status Active
Type Known Issues
Devices
  • FPGA Device Families
Tools
  • ISE Design Suite - 14