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AR# 53364

7 Series FPGA GTX/GTH Transceivers - Recommendations and Settings for SATA Gen 1, Gen 2, Gen 3 Optimal Performance

Description

This answer record discusses the recommended settings and use mode details for optimal performance of Serial ATA (SATA) applications using the Kintex-7/Virtex-7 FPGA GTX and GTH Transceivers.

Solution

1. SATA specification requires Spread Spectrum Clocking (SSC) support with a requirement of +/- 700 ppm offset with 0 to -5000 ppm down spread. 

This requires a properly tuned CDR setting using the 2nd order loop. 

The following optimal RXCDR_CFG settings should be used for this application:

GTX:

SATA line rate RXOUT_DIV RXCDR_CFG
Gen 3, 6 Gb/s 1 72'h03_8000_8BFF_1020_0010
Gen 2, 3 Gb/s 2 72'h03_8800_8BFF_4020_0008
Gen 1, 1.5 Gb/s 4 72'h03_8000_8BFF_4010_0008


GTH
:

SATA line rate  RXOUT_DIV RXCDR_CFG
Gen 3, 6 Gb/s 1 83'h0_0010_07FE_1000_C848_8018
Gen 2, 3 Gb/s 2 83'h0_0008_07FE_0800_C8A0_8118
Gen 1, 1.5 Gb/s 4 83'h0_0004_07FE_0800_C8A0_8118


2. The various scenarios and use cases that require GTX/GTH resets are documented in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476), Chapter 2.

Specifically, for SATA some drives go in and out of electrical idle (OOB detection - assertion/de-assertion of RXELECIDLE) when switching between the different SATA line rates of Gen 1, Gen 2 and Gen 3. 

This is exhibited by only some drives since this is only an optional requirement in the SATA specification.

As a result, proper care must be taken and the end user application must properly reset the CDR and the entire RX to handle going in and out of RXELECIDLE scenarios as per the user guide recommendations. 

This is achieved via resetting the GTRXRESET port.

 

Revision History
05/01/2014 - Updated the GTX RXCDR_CFG settings for SATA Gen 2/Gen 3
12/18/2012 - Initial release

AR# 53364
Date Created 12/18/2012
Last Updated 06/24/2014
Status Active
Type General Article
Devices
  • Virtex-7
  • Kintex-7