1. SATA specification requires Spread Spectrum Clocking (SSC) support with a requirement of +/- 700ppm offset with 0 to-5000 ppm down spread.This requires a properly tuned CDR settingutilizing the 2nd order loop. The followingoptimal RXCDR_CFGsettings should be used for this application:
GTX:
| SATA line rate | RXOUT_DIV | RXCDR_CFG |
|---|---|---|
| Gen 3, 6 Gb/s | 1 | 72'h03_8000_8BFF_2020_0010 |
| Gen 2, 3 Gb/s | 2 | 72'h03_8000_8BFF_4020_0008 |
| Gen 1, 1.5 Gb/s | 4 | 72'h03_8000_8BFF_4010_0008 |
GTH:
| SATA line rate | RXOUT_DIV | RXCDR_CFG |
|---|---|---|
| Gen 3, 6 Gb/s | 1 | 83'h0_0010_07FE_1000_C848_8018 |
| Gen 2, 3 Gb/s | 2 | 83'h0_0008_07FE_0800_C8A0_8118 |
| Gen 1, 1.5 Gb/s | 4 | 83'h0_0004_07FE_0800_C8A0_8118 |
2. The various scenarios and use casesthat requireGTX/GTHresets are documented inthe7 Series FPGAs GTX/GTH Transceivers User Guide (UG476), Chapter 2.
Specifically, for SATAsome drives go in and out of electrical idle (OOB detection - assertion/de-assertion of RXELECIDLE) when switching between the different SATA line ratesof Gen 1, Gen 2 and Gen 3. This is exhibited by only some drives since this is only an optional requirement in the SATA specification.
So, proper care must be taken and the end user applicationmust properly reset theCDR and the entire RX to handlegoing in and out of RXELECIDLE scenarios as per the user guide recommendations. This isachieved via resetting the GTRXRESET port.