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AR# 53377

AXI Bridge for PCI Express - How do I configure the core with non-prefetchable 64-bit BAR?

Description

How do I configure non-prefetchable 64-bit BAR in the AXI Bridge for PCI Express IP (EDK) core or the AXI Memory Mapped To PCI Express (Vivado) core?

Solution

Currently the cores only support prefetchable 64-bit BAR, however the core can be configured to support non-prefetchable 64-bit BAR with the following workaround.

Core file to modify:
   axi_pcie.vhd

Change the following lines in axi_pcie.vhd:

   (Section 1) - Change from:

      constant PCIBAR_PREFETCH_0  : integer := C_PCIEBAR_AS;  --prefetch_config(C_PCIEBAR_AS, 0, 0);
      constant PCIBAR_PREFETCH_1  : integer := C_PCIEBAR_AS;  --prefetch_config(C_PCIEBAR_AS, 0, 0);
      constant PCIBAR_PREFETCH_2  : integer := C_PCIEBAR_AS;  --prefetch_config(C_PCIEBAR_AS, 0, 0);

   - To:

     constant PCIBAR_PREFETCH_0  : integer := 0;  --prefetch_config(C_PCIEBAR_AS, 0, 0);
     constant PCIBAR_PREFETCH_1  : integer := 0;  --prefetch_config(C_PCIEBAR_AS, 0, 0);
     constant PCIBAR_PREFETCH_2  : integer := 0;  --prefetch_config(C_PCIEBAR_AS, 0, 0);

   (Section 2) - Change from:

    assert FALSE
    report "INVALID BAR: 64 bit, non-prefetch NOT ALLOWED"
    severity Warning;

   - To:

    var_out := func_invert(conv_std_logic_vector(((2**pcibar_len_64)-1),64))+x"4";


To apply the workaround, follow the steps below:

For XPS (Xilinx Platform Studio):

   1) Generate an AXI Bridge for PCI Express core with 64-bit BAR selected.
   2) Make the PCIe IP core local (In XPS, right click on the PCIe IP core and click on "Make this IP core local").
   3) Navigate to the <project directory>/pcores/axi_pcie_<core_version>/hdl/vhdl directory.
   4) Edit the axi_pcie.vhd core file according to the instructions above.
   5) Continue Synthesis and Implementation of the project as usual.

For Vivado (OOC - Out Of Context enabled flow):

   1) Generate an AXI Memory Mapped To PCI Express core with 64-bit BAR selected. Ensure that you have completed the "Generate Output Products" step.
   2) Navigate to the <project directory>/<project_name>.srcs/sources_#/ip/<core_name>/axi_pcie_<core_version>/hdl/src/vhdl directory.
   3) Edit the axi_pcie.vhd core file according to the instructions above.

   4) Re-synthesize the core (Right click on the <core_name>_synth_1 under Out-of-Context Module Runs and then choose Launch Runs)
     

53377.png
53377.png



   5) Continue Synthesis and Implementation of the project as usual.

For Vivado (non-OOC - Out Of Context disabled flow):

   1) Generate an AXI Memory Mapped To PCI Express core with 64-bit BAR selected. Ensure that you have completed the "Generate Output Products" step.
   2) Navigate to the <project directory>/<project_name>.srcs/sources_#/ip/<core_name>/axi_pcie_<core_version>/hdl/src/vhdl directory.
   3) Edit the axi_pcie.vhd core file according to the instruction listed above.
   4) Continue the Synthesis and Implementation of the project as usual.

For Vivado (IPI - IP Integrator / Block Design flow):

   Note: This is a two steps process. Step 1 will produce a custom IP that will contain the workaround. Step 2 is an IPI flow with custom IP.  

   Step 1:
   1) Create a new Vivado project with the same device and language selection as the main project.
   2) Generate an AXI Memory Mapped To PCI Express core with 64-bit BAR selected. Ensure that the core has been configured fully to be used in the main project.
   3) In the "Generate Output Products" step, generate a non-OOC flow core (disable Out Of Context selection) and then continue and generate the core.
   4) Navigate to the <project directory>/<project_name>.srcs/sources_#/ip/<core_name>/axi_pcie_<core_version>/hdl/src/vhdl directory.
   5) Edit the axi_pcie.vhd core file according to the instructions above.
   6) Go back to the Vivado project and generate a custom IP from this modified core:
        a) Click Tools -> Create and Package IP
        b) In the Wizard, click Next
        c) Choose "Package your current project" and then click Next
        d) Choose "Include IP Generated Files" and then click Next
        e) On the final page, click Finish
        f)  A new tab (Package IP) should now open.
           Go to the File Groups section and expand Standard -> Synthesis hierarchy.
           Find the following two constraint files; <core_name>_ooc.xdc and axi_pcie_<block location>.xdc.
 
            - For <core_name>_ooc.xdc, set its property as follows:
                  Processing Order : early
                  Used In                  : synthesis implementation out_of_context
                  Scoped to Ref       : <core_name>. For example axi_pcie_0
                  Scoped to Cells    : inst
 
            - For axi_pcie_<block location>.xdc, set its property as follow:
                  Processing Order : early
                  Used In                  : synthesis implementation
                  Scoped to Ref       : <core_name>. For example axi_pcie_0
                  Scoped to Cells    : inst
 
        g) In the Review and Package section, click "Package IP"

   Step 2:
   1) Go to the main project.
   2) Click Tools -> Project Settings -> IP -> Add Repository. Point the repository to the above project's directory: <Custom IP project location>/<project_name>.srcs/sources_#/ip directory. Click OK.
   3) Create a Block Design (IPI).
   4) Choose "Add IP" and the new custom IP should show up here with a name <core_name>_v1_0. The core will no longer be customizable as it has been customized earlier.
   5) Connect the core and then Synthesize and Implement the project as usual.


Revision History:
12/07/2012 - Initial Release
10/12/2014 - Updated for Vivado

Attachments

Associated Attachments

Name File Size File Type
axi_pcie.vhd 115 KB VHD
AR# 53377
Date Created 12/07/2012
Last Updated 12/23/2014
Status Active
Type General Article
IP
  • AXI PCI Express (PCIe)