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AR# 53396

7 Series FPGAs Transceiver Wizard v2.4 - Known Issues and Release Notes

Description

This answer record contains the Known Issues and Release Notes for the 7 series FPGAs Transceiver Wizard v2.4, released with the ISE 14.4 and Vivado 2012.4 design tools.

Solution

1. INTRODUCTION
  This file contains the change log for all released versions of the Xilinx 
  LogiCORE IP core 7 Series FPGAs Transceivers Wizard. 
  
  For the latest core updates, see the product page at:
  For installation instructions for this release, please go to:
  For system requirements, see:

2. DEVICE SUPPORT
  2.1. ISE
    The following device families are supported by the core for this release:
    All 7 Series devices 
  2.2. VIVADO
    All 7 Series devices 

3. NEW FEATURE HISTORY
  3.1 ISE
    v2.4 
    - Support for General ES and Production Silicon for GTX
    - Support for General ES for GTH
    - Support for Initial ES and General ES for GTP
    - Support for Initial ES for GTZ
    - New Protocol Templates added for GTX - CAUI, 10GBASE-KR
    - New Protocol Templates added for GTH - XLAUI, 10GBASE-R
  

    v2.3 
    - Support for General ES and Production Silicon for GTX
    - Support for General ES for GTH
    - Support for Initial ES for GTP
    - Support for Initial ES for GTZ
    - New Protocol Templates added for GTX - 
    - New Protocol Templates added for GTH - Display Port, OC192
  
    - New Protocol Templates added for GTP - CEI-6, Aurora 8B10B, Aurora64B66B
    - New Protocol Templates added for GTZ - Aurora 64B66B
 
    v2.2 
    - Support for GTZ Transceiver
    - Support for General ES and Production Silicon for GTX
    - Support for Initial ES for GTH
    - Support for PCIE Gen1/Gen2 protocol for GTP Transceiver
 
    - Enhanced Example Design for GTP
    - New Protocol Templates added for GTX - JESD204
    - New Protocol Templates added for GTH - Aurora 8B/10B
  
    - New Protocol Templates added for GTP - SRIO Gen1/Gen2
 
    v1.5
    - Support for Initial ES for GTX
 
  3.2 Vivado
    v2.4 
    - Support for General ES and Production Silicon for GTX
    - Support for General ES for GTH
    - Support for Initial ES and General ES for GTP
    - Support for Initial ES for GTZ
    - New Protocol Templates added for GTX - CAUI, 10GBASE-KR
    - New Protocol Templates added for GTH - XLAUI, 10GBASE-R
  

    v2.3 
    - Support for General ES and Production Silicon for GTX
    - Support for General ES for GTH
    - Support for Initial ES for GTP
    - Support for Initial ES for GTZ
    - New Protocol Templates added for GTH - Display Port, OC192
  
    - New Protocol Templates added for GTP - CEI-6, Aurora 8B10B, Aurora64B66B
    - New Protocol Templates added for GTZ - Aurora 64B66B

    v2.2 
    - Support for GTZ Transceiver
    - Support for General ES and Production Silicon for GTX
    - Support for Initial ES for GTH
    - Support for PCIE Gen1/Gen2 protocol for GTP Transceiver
 
    - Enhanced Example Design for GTP
    - New Protocol Templates added for GTX - JESD204
    - New Protocol Templates added for GTH - Aurora 8B/10B
  
    - New Protocol Templates added for GTP - SRIO Gen1/Gen2

    v1.5
    - Support for Initial ES for GTX, including XC7V2000T
 
4. RESOLVED ISSUES

  4.1 ISE
    The following issues are resolved in the indicated IP versions:
    v2.4
      - Increased the line rate of CPLL to 10.3125 Gb/s for GTH devices, -2 and -3 speed grade
      - Removed the RECCLK_MONITOR module from example design.
      - Modified the GT column information in GUI for various GTX and GTH devices 
 
  4.2 Vivado
    The following issues are resolved in the indicated IP versions:
    v2.4
      - Increased the line rate of CPLL to 10.3125 Gb/s for GTH devices, -2 and -3 speed grade
      - Removed the RECCLK_MONITOR module from example design.
      - Modified the GT column information in GUI for various GTX and GTH devices 
 
5. KNOWN ISSUES & LIMITATIONS
  - This version of the Wizard is NOT native Vivado compatible. Hence, Upgrading from earlier versions
    of the IP is not supported in Vivado. To upgrade from v1.5, v1.6, v2.1, v2.2 or v2.3 versions, users
    can use the CORE Generator tool.
  - The Wizard generates Verilog wrappers for GTZ. VHDL is not supported.
  - For GTZ designs, the Wizard supports line rates and reference clocks shown in the GUI.
    No other values are tested or validated in hardware.
  - It is recommended that the Beachfront module generated for GTZ designs should NOT be
    modified by the user. Any edits made by the user might lead to unexpected results.
  - Please note that Vivado flow should be used for implementation of all SSIT devices
  - Please note that the protocol templates provided by the Wizard are not characterized on
    hardware
  - Please refer AR 50890 - www.xilinx.com/support/answers/50890.htm for information
    on how to use the 7 series FPGAs Transceivers Wizard in the Vivado 2012.2/2012.3/2012.4 tools.
  - Please refer AR 43244 - www.xilinx.com/support/answers/43244.htm for information
    on GTX Initial ES Settings
  - Please refer AR 47128 - www.xilinx.com/support/answers/47128.htm for information
    on GTH Initial ES Settings
  - Please refer AR 45360 - www.xilinx.com/support/answers/45360.htm for information
    on GTX General ES Settings
  - Please refer AR 51625 - www.xilinx.com/support/answers/51625.htm for information
    on GTH General ES Settings
  - Please refer AR 51369 - www.xilinx.com/support/answers/51369.htm for information
    on GTP Initial ES Settings
  - For a comprehensive listing of Known Issues for this core, please see the IP
    Release Notes Guide, 
   
    www.xilinx.com/support/documentation/user_guides/xtp025.pdf
 
6. TECHNICAL SUPPORT & FEEDBACK
   To obtain technical support, create a WebCase at www.xilinx.com/support
   Questions are routed to a team with expertise using this product. 
   Feedback on this IP core may also be submitted under the "Leave Feedback"
   menu item in Vivado/PlanAhead.
   Xilinx provides technical support for use of this product when used
   according to the guidelines described in the core documentation, and
   cannot guarantee timing, functionality, or support of this product for
   designs that do not follow specified guidelines.

7. CORE RELEASE HISTORY
Date        By            Version      Description
================================================================================
12/18/2012  Xilinx, Inc.  2.4          ISE 14.4 and Vivado 2012.4.
10/16/2012  Xilinx, Inc.  2.3          ISE 14.3 and Vivado 2012.3.
07/25/2012  Xilinx, Inc.  2.2          ISE 14.2 and Vivado 2012.2.
04/24/2012  Xilinx, Inc.  2.1          ISE 14.1 and Vivado 2012.1; Defense Grade 7 Series and Zynq devices, Automotive 
                                                 Zynq devices.
01/19/2012  Xilinx, Inc.  1.6          ISE 13.4: Minor feature enhancements, completely backward-compatible.
08/19/2011  Xilinx, Inc.  1.5          ISE 13.3
06/22/2011  Xilinx, Inc.  1.4          ISE 13.2: CORE Generator tool flow Support
03/01/2011  Xilinx, Inc.  1.3          Initial release
================================================================================
 
AR# 53396
Date Created 12/10/2012
Last Updated 11/10/2014
Status Active
Type Release Notes
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • 7 Series FPGAs Transceivers Wizard