I run the Artix-7 FPGA Base Targeted Reference design in Vivado Design Suite and I get 10 paths with setup violations, with TSN of -0.478 ns and a pulsewidth violation of WPWS of -0.034 ns. When I investigated further, I noticed that the total delay for the worst path, it was 95% routing. How can I fix this issue?
You can try setting the router effort level to high.
This issue is scheduled to be fixed in the next major release of the software.