Version Found: MIG 7 Series v1.8/1.8.a
Version Resolved: See
(Xilinx Answer 45195)The MIG 7 Series DDR3/DDR2 designs have internal signals that include both KEEP and MAX_FANOUT attributes applied to ensure proper implementation and successful timing. In some cases (2:1 designs with greater than 64-bits, running at the max data rates), this causes the MAX_FANOUT to not be accepted and timing violations to occur.