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AR# 53434 MIG 7 Series DDR3 - Potential timing violations in OCLKDELAY calibration

Description

Version Found: 1.7
Version Resolved: See (Xilinx Answer 45195)

If implementing the MIG 7 Series DDR3 v1.7 design, timing violations might be seen in the OCLKDELAY calibration module. This answer record details why these violations occur and indicates the work-around.

Solution

These timing violations are due to many levels of logic in the OCAL_NEW_DQS_WAIT state. These levels of logic are reduced in the MIG 7 Series v1.8 OCLKDELAY calibration module. If timing violations occur, please update to the new rtl.

Actions

AR# 53434
Date Created 12/11/2012
Last Updated 01/31/2013
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
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