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AR# 53436 MIG 7 Series RLDRAM II - Timing failure from CMD_WR_EN to PRE_FIFO

Description


Version Found: v1.8
Version Resolved and other Known Issues: See (Xilinx Answer 45195)

When implementing the MIG 7 Series RLDRAM II v1.8/v1/8a design, the following timing violations may be seen between the CMD_WR_EN to PRE_FIFO.

Slack (setup path): -0.479ns (requirement - (data path - clock path skew + uncertainty))
Source: u_mig_7series_v1_8/u_mig_7series_v1_8_rld_memc_ui_top_std/u_rld_phy_top/u_phy_write_top/GEN_PHY_CNTRL_INIT.u_qdr_rld_phy_cntrl_init/of_cmd_wr_en (FF)
Destination: u_mig_7series_v1_8/u_mig_7series_v1_8_rld_memc_ui_top_std/u_rld_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_0.u_qdr_rld_phy_4lanes/qdr_rld_byte_lane_D.qdr_rld_byte_lane_D/GEN_PRE_FIFO.u_qdr_rld_pre_fifo/_o32462_48 (FF)

Requirement: 4.444ns
Data Path Delay: 4.288ns (Levels of Logic = 3)
Clock Path Skew: -0.564ns (1.364 - 1.928)
Source Clock: clk rising at 0.000ns
Destination Clock: clk rising at 4.444ns
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.123ns
Phase Error (PE): 0.000ns


Solution


These timing failures can occur as a result of too high a fan-out on the "of_cd_wr_en" and "of_data_wr_en" registers within the qdr_rld_phy_cntrl_init.v module. If these timing failures are seen, the following changes can be made to qdr_rld_phy_cntrl_init.v as a work-around:

Change:

output reg of_cmd_wr_en,
output reg of_data_wr_en

to:

(* keep = "true", max_fanout = 10 *) output reg of_cmd_wr_en /* synthesis syn_maxfan = 10 */ ,
(* keep = "true", max_fanout = 10 *) output reg of_data_wr_en/* synthesis syn_maxfan = 10 */

Revision History
12/18/2012 - Initial release

Actions

AR# 53436
Date Created 12/12/2012
Last Updated 12/12/2012
Status Active
Type
Devices
  • Virtex-7
  • Kintex-7
IP
  • MIG 7 Series
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