Version Found: v1.8
Version Resolved and other Known Issues: See (Xilinx Answer 45195)
When implementing the MIG 7 Series RLDRAM II v1.8/v1/8a design, the following timing violations may be seen between the CMD_WR_EN and PRE_FIFO.
These timing failures can occur as a result of too high a fan-out on the "of_cd_wr_en" and "of_data_wr_en" registers within the qdr_rld_phy_cntrl_init.v module.
If these timing failures are seen, the following changes can be made to qdr_rld_phy_cntrl_init.v as a work-around:
12/18/2012 - Initial release