Version Found: v1.8
Version Resolved and other Known Issues: See (Xilinx Answer 45195)
When implementing the MIG 7 Series RLDRAM II v1.8/v1/8a design, the following timing violations may be seen between the CMD_WR_EN and PRE_FIFO.
Slack (setup path): -0.479ns (requirement - (data path - clock path skew + uncertainty))
These timing failures can occur as a result of too high a fan-out on the "of_cd_wr_en" and "of_data_wr_en" registers within the qdr_rld_phy_cntrl_init.v module.
If these timing failures are seen, the following changes can be made to qdr_rld_phy_cntrl_init.v as a work-around:
Change:
output reg of_cmd_wr_en,
output reg of_data_wr_en
to:
(* keep = "true", max_fanout = 10 *) output reg of_cmd_wr_en /* synthesis syn_maxfan = 10 */ ,
(* keep = "true", max_fanout = 10 *) output reg of_data_wr_en/* synthesis syn_maxfan = 10 */
Revision History
12/18/2012 - Initial release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45195 | MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions | N/A | N/A |
| AR# 53436 | |
|---|---|
| Date | 01/26/2015 |
| Status | Active |
| Type | Known Issues |
| Devices |
|
| IP |
|