53465

Why does my DSP Digital Communications core fail to simulate with: Error: Failed to find design work <Core name>?

This will happen when trying to simulate one of the listed cores below, with anything other than the Vivado Simulator.

This is a known issue that will be resolved in a future version of the Vivado tool.

To work around this issue, use the Vivado Simulator, or contact the Xilinx Technical Support.

IP DSP Digital Communications

LogiCORE LTE Fast Fourier Transform
LogiCORE LTE UL Channel Decoder
LogiCORE LTE Rach Detector
LogiCORE LTE PUCCH Receiver
LogiCORE Linear Algebra Toolkit
LogiCORE IP Peak Cancellation Crest Factor Reduction (PC-CFR)
LogiCORE MIMO Encoder
LogiCORE 3GPP LTE Turbo Encoder
LogiCORE 3GPP Turbo Encoder

AR# 53465
Date Created	01/02/2013
Last Updated	01/02/2013
Status	Active
Type
Devices	FPGA Device Families
Tools	Vivado - 2012.4
IP	3GPP LTE UL Channel Decoder 3GPP LTE Turbo Encoder 3GPP LTE RACH Detector More 3GPP LTE PUCCH Receiver 3GPP LTE MIMO Encoder LTE Fast Fourier Transform Less

AR# 53465 2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with Error: Failed to find design work <Core name>?

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AR# 53465 2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with Error: Failed to find design work <Core name>?

Description

Solution

Actions