UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 53505

Vivado 2012.x - Vivado Synthesis - Does Vivado Synthesis infer a block RAM on an asynchronous reset output register?

Description

Does Vivado Synthesis infer a block RAM if an asynchronous reset is used on an output register?

Solution

Vivado synthesis does not infer a block RAM when an asynchronous reset is used on an output register. Here is an example:

module test # (
parameter data_w = 32,
addr_w = 9
)
(
input rst_n,
input wrclk,
input rdclk,
input [addr_w-1:0] wraddr,
input [addr_w-1:0] rdaddr,
input [data_w-1:0] data,
input wren,
output reg [data_w-1:0] dout
);

reg [data_w-1:0] mem [(1<<addr_w)-1:0];
reg [data_w-1:0] wrdata_r;
reg [addr_w-1:0] wraddr_r,rdaddr_r;
reg wren_r;


always @ (posedge wrclk)
begin
if(wren)
mem[wraddr] <= data;
end

always @ (posedge rdclk or negedge rst_n)
begin
if(~rst_n)
begin
begin
rdaddr_r <= 0;
dout <= 0;
end
end
else
begin
rdaddr_r <= rdaddr;
dout <= mem[rdaddr_r];
end
end

endmodule

Vivado Synthesis currently infers LUTRAM's and inference of block RAM is not currently supported when an asynchronous reset is present onan output register.

AR# 53505
Date Created 12/14/2012
Last Updated 12/14/2012
Status Active
Type Known Issues
Tools
  • Vivado