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AR# 53522

Triple Rate SDI - How many cycles do the crc_err_a and crc_err_b remain asserted for?

Description

How many cycles do the crc_err_a and crc_err_b remain asserted for?

According to the following documentation, it is only asserted for one cycle, but the code appears to be for one line?

  • XAPP1014 - Audio/Video Connectivity Solutions for Virtex-5 FPGAs
  • XAPP1076 - Implementing Triple-Rate SDI with Spartan-6 FPGA GTP Transceivers
  • UG823 - LogiCORE IP Virtex-6 FPGA Triple-Rate SDI v1.0 User Guide
  • UG824 - LogiCORE IP Spartan-6 FPGA Triple-Rate SDI v1.0 User Guide
  • PG071 - SMPTE SD/HD/3G-SDI v1.0 Product Guide v1.0

Solution

The crc_err_a and crc_err_b are asserted for each line in which a CRC error is detected. 

The CRC is only sent once per line, and only checked once per line.

Please see (Xilinx Answer 40473) for a detailed list of LogiCORE IP Triple Rate SDI Release Notes and Known Issues.
Please see (Xilinx Answer 42805) for a detailed list of LogiCORE IP Spartan-6 FPGA Triple-Rate SDI Release Notes and Known Issues.
Please see (Xilinx Answer 50905) for a detailed list of LogiCORE IP SMPTE SD/HD/3G-SDI Release Notes and Known Issues.

Linked Answer Records

Master Answer Records

AR# 53522
Date Created 12/18/2012
Last Updated 08/26/2014
Status Active
Type General Article
IP
  • Spartan-6 FPGA Triple-Rate SDI
  • Virtex-6 FPGA Triple-Rate SDI
  • SMPTE SD/HD/3G-SDI