Vivado Synthesis currently generates multiple drivers on a HDL code containing keep or syn_keep attribute on multi-bit register that is assigned in a bit-slice way in more than two processes or always block statement.
What is the reason for this behavior?
Following is a detail description of the problem.
For example,there is an inherent presence of KEEP or syn_keep attribute on a 3-bit register arst_d in a HDL code that is assigned in a bit-slice way in more than two processes or always block statements, Vivado Synthesis currently will generate mult-driver critical warnings as follows:
CRITICAL WARNING: [Synth 8-3352] multi-driven net \u_fpga/u_proj/eth_switch_ctrl.u_glbl_rst_gp_reg_clk/arst_d [0] with 1st driver pin '\u_fpga/u_proj/eth_switch_ctrl.u_glbl_rst_gp_reg_clk/arst_d_reg[0]__0 /Q'
CRITICAL WARNING: [Synth 8-3352] multi-driven net \u_fpga/u_proj/eth_switch_ctrl.u_glbl_rst_gp_reg_clk/arst_d [0] with 2nd driver pin '\u_fpga/u_proj/eth_switch_ctrl.u_glbl_rst_gp_reg_clk/arst_d_reg[0] /Q'
The reason for these multiple drivers is that the keep or syn_keep attribute on the 3-bit register that was assigned in more than 2 processes in a bit-slice manner blocked the tool from performing analysis on this 3-bit register. This resulted in a multiple driver situation.
To work around this issue, remove the keep or syn_keep attribute present in the code. This will resolve the multiple driver conflict scenario and the critical warning messages will not be generated. Also, multiple drivers will not be generated if the code was rewritten to be in a single process or always blocks. This can also be considered as another option for a work around. This issue will be fixed in one of the future Vivado Synthesis releases. A specific fix date has not been determined for this issue at this time.