Therequired sequences to follow for issuing GTRXRESET, RXPMARESET, or RXRATE in the Artix-7 GTP Production Transceivers are documented below. These reset sequences canbe also used on General ES silicon but are not required.

These sequences are implemented in the wrapper generated by 7 Series FPGAs Transceivers Wizard v2.5 in the"ISE 14.4.1 Device Pack" tool version. The reset sequenceswill be added to the next revision of the 7 Series FPGA GTP Transceiver User Guide (UG482).

In these sequences, "user_*" denotes user input.This signal was previously connected directly to the GT primitive.It will now trigger an alternative reset sequence as described below.
"gt_*" denotes connection to GT primitive. The following diagram indicates where this new sequence fits in.
"DRP wr" denotes the function of performing a DRP write to address 9'h011. The exact DRP transaction is not shown.

1. GTRXRESET:

Thefollowingreset sequence must be followedwhen the user wants to perform GTRXRESET.

1. User triggers a reset request by asserting user_GTRXRESET.
2. Set and hold gt_GTRXRESET High. This will cause gt_RXPMARESETDONE to go Low.
3. Issue DRP write to the GTPE2_CHANNEL primitive, DRP address 9'h011, and set bit[11] to 1'b0.
4. In order to ensure only bit[11] of DRP address 9h'011 is modified, it is best to perform a read-modify-write function.
5. Upon DRP write completion and user_GTRXRESET detected as Low, set and hold gt_GTRXRESET Low. If user_GTRXRESET remains asserted upon completion of the DRP write, continue to assert gt_GTRXRESET until user_GTRXRESET is Low.
6. Wait for falling edge of gt_RXPMARESETDONE.
7. Issue DRP write to the GTPE2_CHANNEL primitive, DRP address 9'h011, restoring the original setting for bit[11]. The completion of this DRP write must occur before gt_RXPMARESETDONE switches from Low to High.gt_RXPMARESETDONE will stay Low for a minimum of 0.66 us.

Notes:

1. Make sure gt_GTRXRESET is output of a register.
2. Make sure RXPMARESET_TIME is set to 5'h3. This should be the default setting
3. The sequence above will only simulate properly if SIM_GTRESET_SPEEDUP is set to FALSE. If SIM_GTRESET_SPEEDUP is set to TRUE, the above sequence must be bypassed.
   

1. User triggers a RXPMARESET request by asserting user_RXPMARESET
2. Issue DRP write to the GTPE2_CHANNEL primitive, DRPADDR 9h011, and set bit[11] to 1b0
3. In order to ensure only bit[11] of DRPADDR 9h011 is modified, it is best to perform a read-modify-write function.
4. Upon DRP write completion, set and hold gt_RXPMARESET High.
5. Wait for RXPMARESETDONE to go Low
6. Issue DRP write to the GTPE2_CHANNEL primitive, DRPADDR 9h011, restoring the original setting for bit[11].
7. Upon DRP write completion and user_RXPMARESET detected as Low, set and hold gt_RXPMARESET Low. If user_RXPMARESET remains asserted upon completion of the DRP write, continue to assert gt_RXPMARESET until user_RXPMARESET is Low.
   

Note: Make sure gt_RXPMARESET is output of a register.

3.RXRATE:

Thefollowingsequence must be followedwhen the user wants to trigger RX rate change via RXRATE.

Steps:

1. User triggers a RX rate change request by changing user_RXRATE.
2. Issue DRP write to the GTPE2_CHANNEL primitive, DRPADDR 9h011, set bit[11] to 1b0.
3. In order to ensure only bit[11] of DRPADDR 9h011 is modified, it is best to perform a read-modify-write function.
4. Upon DRP write completion, set gt_RXRATE to the value of user_RXRATE.
5. Wait for RXPMARESETDONE to go Low
6. Issue DRP write to the GTPE2_CHANNEL primitive, DRPADDR 9h011, restoring the original setting for bit[11]. The completion of this DRP write must occur before RXPMARESETDONE switches from Low to High. RXPMARESETDONE will stay Low for a minimum of 0.66 us.

Note: The sequence above will only simulate properly if SIM_GTRESET_SPEEDUP is set to FALSE. If SIM_GTRESET_SPEEDUP is set to TRUE, the above sequence must be bypassed.

GTP Attribute: