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AR# 53732

14.4 - Vivado/XPS - Vivado Project-less Flow Tutorial for XPS/XMP Source


Project-less flow is for the users who want to manage their own design data or track design state. In this flow, Vivado tool reads the various source files and implements the design through the entire flow in-memory. At any stage of the implementation process, users can generate a variety of reports based on their script. When running in project-less mode,
it is also important to note that this mode does not enable project-based features such as source file and run management, cross-probing back to source files, design state reporting, and et cetera. Essentially, each time a source file is updated on the disk, users must know about it and reload the design. There are no default reports or intermediate files created within the project-less mode. Users need to havetheir script control the creation of reports with Tcl commands.
Vivado version 2012.4 or later


Flow Diagram


Project-Less Flow Example

Vivado tool can be invoked in Tcl mode instead of usual GUI mode by issuing following commands in console. This will start Vivado in command line interface and returns vivado% prompt. The recommended approachin this mode is to create a Tcl script and source it from the Vivado prompt:
vivado -mode tcl
The first step is to add in the source file for an embedded design.
vivado% add_files -norecurse <absolute path to the XMP file>
The user may see a critical warning when the XMP file is added. This is because of the mismatch in the default device Vivado loads and the device set in the XMP file. This is benign and will not affect since the device will be set explicitly in the synth_design stage as mentioned later.
Once embedded source is added successfully, users need to addtheir top-level RTL files and any top-level XDC constraints.
vivado% read_verilog <top-level>.v
vivado% read_xdc <top-level>.xdc
The user can also create top level HDL wrapper file using the command below since a XMP source cannot be synthesized directly.
vivado% make_wrapper-files[get_files <path to XMP file>] -top -fileset [get_filesets sources_1] -import
vivado% read_verilog <absolute path to the generated wrapper file>
This creates a top-level HDL file and adds it to the source list. The top-level wrapper file is created in the same location as the XMP file.
For a MicroBlaze based design, the user should populate the I-LMB with either a Bootloop ortheir own executable in ELF format.
An example Bootloop ELF can be found here: $XILINX_EDK/sw/lib/microblaze/mb_bootloop_le.elf.
The user then needs to add the ELF and associate it with the MicroBlaze instance. The following steps would do this.
vivado% add_files <ELF file Targeted to BRAM with .elf extension>
vivado% set_property MEMDATA.ADDR_MAP_CELLS {<XPS system instance name>/microblaze_0} [get_files <BRAM Targeted ELF File>]
If the user design has multiple levels of hierarchy,they need to ensure that the correct hierarchy is provided.
After this, the user needs to go through the usual synthesis, Place and Routesteps to get the design implemented. One aspect that needs to be kept in mind is that for the synthesis (synth_design) step, the user needs to provide the target part as the default target part, whichmay not be the same as the desired one.
In case the user wants specific reports to be generated or check-points to be dumped at certain stages of the design implementation,they need to ensure that the appropriate commands are added to the script.
Once the design is routed user can generate a bitstream by invoking tcl procedure write_bitstream with filename having .bit extension. The bitstream will have the BRAM contents populated with the ELF data.
vivado% write_bitstream <bitfile name>
For users who would like to export the hardware system to SDK, they need to use the following command:
vivado% export_hardware [get_files <Path to XMP file>] -dir <Absolute Export Directory Path>
The followingis a template scriptthat can be used to execute the project-less flow for XPS/XMP source:
add_files <Absolute path to XMP file>
vivado% read_verilog <top-level>.v *
vivado% read_xdc <top-level>.xdc *
add_files <ELF file Targeted to BRAM with .elf extension>
set_property MEMDATA.ADDR_MAP_CELLS {{<XPS system instance name>/microblaze_0} [get_files <BRAM Targeted ELF File>]
synth_design -part <part_name> -top <top-level module name>
write_bitstream system.bit
export_hardware [get_files <Absolute path to XMP file>] -dir <Absolute Export Directory Path>
* -> if Top Level Stub does not exist, use following commands to generate a top-level wrapper for Embedded Source:
make_wrapper-files[get_files <path to XMP file>] -top -fileset [get_filesets sources_1] -import
read_verilog <absolute path to the generated wrapper file>
Users can source this script after updating it to their needs on the Vivado Tcl prompt:
vivado% source <user_script_for project_less_flow>.tcl


AR# 53732
Date Created 01/10/2013
Last Updated 03/07/2013
Status Active
Type General Article
  • Vivado - 2012.4
  • EDK - 14.4