This Design Advisory Answer Record applies to all of the following cores:
Due to incorrect DRP write access of the GT registers from the wrappers of the cores listed above, it has been found that no clock is output on TXOUTCLK at cold temperature. This issue is caused due to assertion of DRP_WE for multiple clock cycles resulting in spurious writes to GT registers through the DRP ports.
DRP_WE must be enabled for only one clock cycle. This requirement is addressed in (Xilinx Answer 53788).
To prevent this issue from occurring, all customers using the cores listed above must make the following changes in <core_name>_pipe_drp.v and <core_name>_qpll_drp.v files.
assign DRP_WE = (fsm == FSM_WRITE) || (fsm == FSM_WRDY);
assign DRP_WE = (fsm == FSM_WRITE);
If you had created a default design in XPS with v1.06.a core, the name of the corresponding files will be:
01/21/2013 - Initial release